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Z8F082x/Z8F081x/Z8F042x/ Z8F041x
Z8 Encore!(R) Z8F082x Series Microcontrollers with Flash Memory and 10-Bit A/D Converter
Product Specification
PS019707-1003 Preliminary
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. (c)2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
PS019707-1003
Preliminary
Disclaimer
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
iii
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contol Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset and STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PS019707-1003
Preliminary
Table of Contents
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
iv
Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . . . . . . STOP Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-C Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-C Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 33 33 33 34 35 35 35 36 37 37 37 37 38 39 40 40 41 46 47 48 48 48 50 50 50 51 51 51 52 52 53 54 55 56 57 58 59 60 60 60
PS019707-1003
Preliminary
Table of Contents
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
v
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0-1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0-1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0-1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . . . Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiprocessor (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
61 61 69 69 69 69 70 72 73 75 75 75 76 76 77 78 78 79 81 81 81 82 82 83 84 85 85 87 87 88 89 91 92 92 93 93 95 95 98 99
PS019707-1003
Preliminary
Table of Contents
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Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102 102 102 103 103 104 106 107 107 107 108 109 110 112 112 113 113 114 114 114 115 116 118 119 120 121 121 121 121 122 122 123 124 125 126 127 127 128 129 130
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I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCDCNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI MASTER Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI SLAVE Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
154 154 155 156 156 157 157 158 159 163 163 165 167 167 167 167 169 171 171 173 175 177 180 181 182 183 184 185 186 188 188 189 189 192 193 197 207 208 212
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Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Z8 Encore!(R) Product Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Problem Description or Suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
216 218 219 219 219 219 219 219 220 220 221 222
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Z8 Encore!(R) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Z8F0821 and Z8F0421 in 20-Pin SSOP and PDIP Packages . . . . . . . . . . . . 7 Z8F0822 and Z8F0422 in 28-Pin SOIC and PDIP Packages . . . . . . . . . . . . 7 Z8F0811 and Z8F0411 in 20-Pin SSOP and PDIP Packages . . . . . . . . . . . . 8 Z8F0812 and Z8F0412 in 28-Pin SOIC and PDIP Packages . . . . . . . . . . . . 8 Power-On Reset Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 11. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 12. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . . 83 Figure 13. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . . 83 Figure 14. UART Asynchronous Multiprocessor Mode Data Format . . . . . . . . . . . . . 87 Figure 15. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) . 89 Figure 16. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . . 91 Figure 17. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 102 Figure 18. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 19. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 20. SPI Configured as a Master in a Single Master, Single Slave System . . . 107 Figure 21. SPI Configured as a Master in a Single Master, Multiple Slave System . . 108 Figure 22. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 23. SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 24. SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 25. 7-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . 123 Figure 26. 10-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . 124 Figure 27. Receive Data Transfer Format for a 7-Bit Addressed Slave . . . . . . . . . . . 125 Figure 28. Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . 126 Figure 29. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 134 Figure 30. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 31. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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List of Figures
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Figure 32. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 33. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 35. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . Figure 36. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . Figure 37. Typical Oscillator Frequency as a Function of the R and C Values . . . . . Figure 38. ICC Versus System Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 39. ICC Versus System Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 40. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 41. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 42. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 43. SPI MASTER Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 44. SPI SLAVE Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 45. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 46. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 47. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 48. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 49. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 50. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 51. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 52. 20-Pin Small Shrink Outline Package (SSOP) . . . . . . . . . . . . . . . . . . . . . Figure 53. 20-Pin Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . Figure 54. 28-Pin Small Outline Integrated Circuit Package (SOIC) . . . . . . . . . . . . . Figure 55. 28-Pin Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . .
154 155 156 168 169 170 174 175 180 181 182 183 184 185 186 187 207 208 210 211 212 213 214 215
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List of Figures
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Z8F082x Family Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Z8F082x Family Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Z8F082x Family Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Z8F082x Family Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset and STOP Mode Recovery Characteristics and Latency . . . . . . . . . . 29 Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STOP Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . 33 Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 37 Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Port A-C GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . 40 Port A-C Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Port A-C Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Port A-C Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 42 Port A-C Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Port A-C High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 44 Port A-C STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . 45 Port A-C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Port A-C Pull-Up Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Port A-C Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 55 IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 56 IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 57 IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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List of Tables
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
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Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69.
IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 57 IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 58 IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 58 Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Timer 0-1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Timer 0-1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Timer 0-1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 71 Timer 0-1 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . . 71 Timer 0-1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 72 Timer 0-1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 72 Timer 0-1 Control Register (TxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . 76 Watch-Dog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . 78 Watch-Dog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . 79 Watch-Dog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 80 Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 80 UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 UART Status 0 Register (U0STAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 UART Status 1 Register (U0STAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 UART Control 0 Register (U0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 UART Control 1 Register (U0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . . . . . 98 UART Baud Rate High Byte Register (U0BRH) . . . . . . . . . . . . . . . . . . . . 99 UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . . . . . . 99 UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . . 110 SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . . . . . . . . . . . . . . 120 SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . 120 I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
PS019707-1003
Preliminary
List of Tables
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
xiv
Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104.
I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . . ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data High Byte Register (ADCDH) . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Low Bits Register (ADCDL) . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z8F082x family Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . Option Bits At Program Memory Address 0000H . . . . . . . . . . . . . . . . . . Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . . . . . . OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Oscillator Specifications (20MHz Operation) . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128 129 131 131 132 132 136 137 138 139 139 141 145 146 147 148 149 149 151 152 156 159 164 165 168 171 173 175 177 177 178 178 180 181 182
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Preliminary
List of Tables
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
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Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125.
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Syntax Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Syntax Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
183 184 185 186 187 189 189 190 191 192 193 194 194 195 195 196 196 197 197 209 216
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List of Tables
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Manual Objectives
This Product Specification provides detailed operating information for the Z8F082x, Z8F081x, Z8F042x, and Z8F041x devices within the Z8 Encore!(R) Microcontroller (MCU) family of products. Within this document, the Z8F082x, Z8F081x, Z8F042x, and Z8F041x are referred to collectively as Z8 Encore!(R) or the Z8F082x family unless specifically stated otherwise.
About This Manual
ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that there are different styles of learning. Therefore, we have designed this Product Specification to be used either as a how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use: Courier Typeface Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the Courier typeface. Where the use of the font is not indicated, as in the Index, the name of the entity is presented in upper case.
*
Example: FLAGS[1] is smrf.
Hexadecimal Values Hexadecimal values are designated by uppercase H suffix and appear in the Courier typeface.
*
Example: R1 is set to F8H.
Brackets The square brackets, [ ], indicate a register or bus.
*
Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant bit, and R1[0] is the least significant bit.
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Braces The curly braces, { }, indicate a single register or bus created by concatenating some combination of smaller registers, buses, or individual bits.
*
Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer (RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the 12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses The parentheses, ( ), indicate an indirect register address lookup.
*
Example: (R1) is the memory location referenced by the address contained in the Working Register R1.
Parentheses/Bracket Combinations The parentheses, ( ), indicate an indirect register address lookup and the square brackets, [ ], indicate a register or bus.
*
Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear The word set implies that a register bit or a condition contains a logical 1. The words reset or clear imply that a register bit or a condition contains a logical 0. When either of these terms is followed by a number, the word logical may not be included; however, it is implied. Notation for Bits and Similar Registers A field of bits within a register is designated as: Register[n:n].
*
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, lsb and msb, mean least significant bit and most significant bit, respectively. Use of Initial Uppercase Letters Initial uppercase letters designate settings and conditions in general text.
* *
Example 1: The receiver forces the SCL line to Low. Example 2: The Master can generate a Stop condition to abort the transfer.
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Use of All Uppercase Letters The use of all uppercase letters designates the names of states, modes, and commands.
* * *
Example 1: The bus is considered BUSY after the Start condition. Example 2: A START command triggers the processing of the initialization sequence. Example 3: STOP mode.
Bit Numbering Bits are numbered from 0 to n-1 where n indicates the total number of bits. For example, the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that all users understand the following safety terms, which are defined here. Caution: Indicates a procedure or file may become corrupted if the user does not follow directions.
Trademarks
ZiLOG, eZ8, Z8 Encore!, and Z8 are trademarks of ZiLOG, Inc. in the U.S.A. and other countries. All other trademarks are the property of their respective corporations.
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Introduction
The Z8 Encore!(R) MCU family of products are the first in a line of ZiLOG microcontroller products based upon the new 8-bit eZ8 CPU. The Z8F082x/Z8F081x/Z8F042x/Z8F041x products, hereafter referred to collectively as the Z8F082x family, expand upon ZiLOG's extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field.The new eZ8 CPU is upward compatible with existing Z8(R) instructions. The rich peripheral set of the Z8 Encore!(R) makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors.
Features * * * * * * * * * * * * * * * * *
eZ8 CPU Up to 8KB Flash memory with in-circuit programming capability 1KB register RAM Optional 2- to 5-channel, 10-bit analog-to-digital converter (ADC) Full-duplex UART I2C Serial peripheral interface (SPI) Infrared Data Association (IrDA)-compliant infrared encoder/decoders Two 16-bit timers with capture, compare, and PWM capability Watch-Dog Timer (WDT) with internal RC oscillator 11-19 I/O pins depending upon package Programmable priority interrupts On-Chip Debugger Voltage Brown-out Protection (VBO) Power-On Reset (POR) 2.7-3.6V operating voltage with 5V-tolerant inputs 0 to +70C standard temperature and -40 to +105C extended temperature operating ranges
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Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the Z8F082x family product line.
Table 1. Z8F082x Family Part Selection Guide 16-bit Timers with PWM 2 2 2 2 2 2 2 2 Package Pin Counts ADC Inputs 5 2 0 0 5 2 0 0 UARTs with IrDA 1 1 1 1 1 1 1 1 I2C 1 1 1 1 1 1 1 1 1 X 1 X X 1 X X SPI 1 X X 20 28 X
Part Number Z8F0822 Z8F0821 Z8F0812 Z8F0811 Z8F0422 Z8F0421 Z8F0412 Z8F0411
Flash (KB) 8 8 8 8 4 4 4 4
RAM (KB) 1 1 1 1 1 1 1 1
I/O 19 11 19 11 19 11 19 11
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Block Diagram
Figure 1 illustrates the block diagram of the architecture of the Z8F082x family devices.
Crystal Oscillator
On-Chip Debugger POR/VBO & Reset Controller
eZ8 CPU System Clock
Interrupt Controller
WDT with RC Oscillator
Memory Busses Register Bus
Timers
UART
I2C
SPI
ADC
Flash Controller
RAM Controller
IrDA
Flash Memory
RAM
GPIO
Figure 1. Z8 Encore!(R) Block Diagram
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CPU and Peripheral Overview
eZ8 CPU Features
The eZ8, ZiLOG's latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8(R) instruction set. The eZ8 CPU features include:
* * * * * * * * * * *
Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8(R) code Expanded internal Register File allows access of up to 4KB New instructions improve execution efficiency for code developed using higher-level programming languages, including C Pipelined instruction fetch and execution New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL New instructions support 12-bit linear addressing of the Register File Up to 10 MIPS operation C-Compiler friendly 2-9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual available for download at www.zilog.com.
General Purpose I/O
The Z8F082x, Z8F081x, Z8F042x, and Z8F041x feature 11 to 19 port pins (Ports A-C) for general purpose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is individually programmable.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a 10bit binary number. The ADC accepts inputs from 2 to 5 different analog input sources.
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UART
The UART is full-duplex and capable of handling asynchronous data transfers. The UART supports 8- and 9-bit data modes and selectable parity.
I2C
The inter-integrated circuit (I2C(R)) controller makes the Z8 Encore!(R) compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line.
Serial Peripheral Interface
The serial peripheral interface (SPI) allows the Z8 Encore!(R) to exchange data between other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Timers
Two 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes.
Interrupt Controller
The Z8F082x/Z8F081x/Z8F042x/Z8F041x products support up to 18 interrupts. These interrupts consist of 7 internal peripheral interrupts and 11 general-purpose I/O pin interrupt sources. The interrupts have 3 levels of programmable interrupt priority.
Reset Controller
The Z8F082x family products can be reset using the RESET pin, power-on reset, WatchDog Timer (WDT), STOP mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8F082x family products feature an integrated On-Chip Debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming the Flash, setting breakpoints and executing code. A single-pin interface provides communication to the OCD.
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Signal and Pin Descriptions
Overview
The Z8F082x family products are available in a variety of packages styles and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information regarding the physical package specifications, please refer to the chapter Packaging on page 212.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8F082x family product line.
Table 2. Z8F082x Family Package Options 20-pin SSOP and PDIP 28-pin SOIC and PDIP X X X X X X X X
Part Number Z8F0822 Z8F0821 Z8F0812 Z8F0811 Z8F0422 Z8F0421 Z8F0412 Z8F0411
10-bit ADC Yes Yes No No Yes Yes No No
Pin Configurations
Figures 2 through 5 illustrate the pin configurations for all of the packages available in the Z8F082x/Z8F081x/Z8F042x/Z8F041x MCU family. Refer to Table 4 for a description of the signals. Note: The analog input alternate functions (ANAx) are not available on the Z8F081x and Z8F041x
devices.
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PA6 / SCL PA7 / SDA RESET VSS XIN XOUT VDD PA0 / T0IN PA1 / T0OUT PA2 / DE0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PC0 / T1IN PB0 / ANA0 PB1 / ANA1 VREF AVSS AVDD DBG PA5 / TXD0 PA4 / RXD0 PA3 / CTS0
Figure 2. Z8F0821 and Z8F0421 in 20-Pin SSOP and PDIP Packages
PC0 / T1IN PA6 / SCL PA7 / SDA RESET VSS XIN XOUT VDD PC5 / MISO PC4 / MOSI PC3 / SCK PC2 / SS PA0 / T0IN PA1 / T0OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PB0 / ANA0 PB1 / ANA1 PB2 / ANA2 PB3 / ANA3 PB4 / ANA4 VREF AVSS AVDD DBG PC1 / T1OUT PA5 / TXD0 PA4 / RXD0 PA3 / CTS0 PA2 / DE0
Figure 3. Z8F0822 and Z8F0422 in 28-Pin SOIC and PDIP Packages
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PA6 / SCL PA7 / SDA RESET VSS XIN XOUT VDD PA0 / T0IN PA1 / T0OUT PA2 / DE0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PC0 / T1IN PB0 PB1 No Connect AVSS AVDD DBG PA5 / TXD0 PA4 / RXD0 PA3 / CTS0
Figure 4. Z8F0811 and Z8F0411 in 20-Pin SSOP and PDIP Packages
PC0 / T1IN PA6 / SCL PA7 / SDA RESET VSS XIN XOUT VDD PC5 / MISO PC4 / MOSI PC3 / SCK PC2 / SS PA0 / T0IN PA1 / T0OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PB0 PB1 PB2 PB3 PB4 No Connect AVSS AVDD DBG PC1 / T1OUT PA5 / TXD0 PA4 / RXD0 PA3 / CTS0 PA2 / DE0
Figure 5. Z8F0812 and Z8F0412 in 28-Pin SOIC and PDIP Packages
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Signal Descriptions
Table 3 describes the Z8F082x family signals. Refer to the section Pin Configurations on page 6 to determine the signals available for the specific package styles.
Table 3. Signal Descriptions Signal Mnemonic I/O Description
General-Purpose I/O Ports A-H PA[7:0] PB[4:0] PC[5:0] I2C Controller SCL I/O Serial Clock. This open-drain pin clocks data transfers in accordance with the I2C standard protocol. This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SCL function, this pin is open-drain. Serial Data. This open-drain pin transfers data between the I2C and a slave. This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SDA function, this pin is open-drain. I/O I/O I/O Port C. These pins are used for general-purpose I/O. Port B. These pins are used for general-purpose I/O. Port C. These pins are used for general-purpose I/O.
SDA
I/O
SPI Controller
SS
I/O
Slave Select. This signal can be an output or an input. If the Z8 Encore!(R) is the SPI master, this pin may be configured as the Slave Select output. If the Z8 Encore!TM is the SPI slave, this pin is the input slave select. It is multiplexed with a general-purpose I/O pin. SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore!(R) is the SPI master, this pin is an output. If the Z8 Encore!(R) is the SPI slave, this pin is an input. It is multiplexed with a general-purpose I/O pin. Master Out Slave In. This signal is the data output from the SPI master device and the data input to the SPI slave device. It is multiplexed with a general-purpose I/O pin. Master In Slave Out. This pin is the data input to the SPI master device and the data output from the SPI slave device. It is multiplexed with a general-purpose I/O pin.
SCK
I/O
MOSI
I/O
MISO
I/O
UART Controllers TXD0 RXD0 O I Transmit Data. This signal is the transmit outputs from the UART and IrDA. The TXD signals are multiplexed with general-purpose I/O pins. Receive Data. This signal is the receiver inputs for the UART and IrDA. The RXD signals are multiplexed with general-purpose I/O pins.
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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O I O Description Clear To Send. This signal is control inputs for the UART. The CTS signals are multiplexed with general-purpose I/O pins. Driver Enable. This signal allows automatic control of external RS-485 drivers. This signal is approximately the inverse of the TXE (Transmit Empty) bit in the UART Status 0 register. The DE signal may be used to ensure the external RS-485 driver is enabled when data is transmitted by the UART.
CTS0 DE0
Timers T0OUT / T1OUT T0IN / T1IN Analog ANA[4:0] VREF I I Analog Input. These signals are inputs to the analog-to-digital converter (ADC). The ADC analog inputs are multiplexed with general-purpose I/O pins. Analog-to-digital converter reference voltage input. As an output, the VREF signal is not recommended for use as a reference voltage for external devices. If the ADC is configured to use the internal reference voltage generator, this pin should be left unconnected or capacitively coupled to analog ground (AVSS). O I Timer Output 0-1. These signals are output pins from the timers. The Timer Output signals are multiplexed with general-purpose I/O pins. Timer Input 0-1. These signals are used as the capture, gating and counter inputs. The Timer Input signals are multiplexed with general-purpose I/O pins.
Oscillators XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. In addition, this pin is used with external RC networks or external clock drivers to provide the system clock to the system. External Crystal Output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. When the system clock is referred to in this manual, it refers to the frequency of the signal at this pin. This pin must be left unconnected when not using a crystal.
XOUT
O
On-Chip Debugger DBG
Caution:
I/O
Debug. This pin is the control and data input and output to and from the On-Chip Debugger. This pin is open-drain. For operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be supplied with power and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must have an external pull-up resistor to ensure proper operation.
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Table 3. Signal Descriptions (Continued) Signal Mnemonic Reset I/O Description
RESET
Power Supply VDD AVDD VSS AVSS
I
RESET. Generates a Reset when asserted (driven Low).
I I I I
Digital Power Supply. Analog Power Supply. Must be powered up and grounded to VDD, even if not using analog features. Digital Ground. Analog Ground. Must be grounded and connected to VSS, even if not using analog features.
Pin Characteristics
Table 4 provides detailed information on the characteristics for each pin available on the Z8F082x family products. Data in Table 4 is sorted alphabetically by the pin symbol mnemonic.
Table 4. Pin Characteristics Schmitt Active Low or Tri-State Internal Pull-up Trigger Reset or Pull-down Input Direction Active High Output N/A N/A I I I I I N/A N/A N/A N/A N/A N/A N/A N/A Low N/A N/A N/A N/A Yes Yes Yes Yes N/A N/A N/A No No No Programmable Pull-up Programmable Pull-up Programmable Pull-up Pull-up No No No No Yes Yes Yes Yes Yes No No
Symbol Mnemonic AVDD AVSS DBG PA[7:0] PB[4:0] PC[5:0] RESET VDD VREF
Direction N/A N/A I/O I/O I/O I/O I N/A Analog
Open Drain Output N/A N/A Yes Yes, Programmable Yes, Programmable Yes, Programmable N/A N/A N/A
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Table 4. Pin Characteristics (Continued) Active Low Schmitt Reset or Tri-State Internal Pull-up Trigger Direction Active High Output or Pull-down Input N/A I O N/A N/A N/A N/A N/A No No No No No No No
Symbol Mnemonic VSS XIN XOUT
Direction N/A I O
Open Drain Output N/A N/A No
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Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
* * *
The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O port control registers. The Program Memory contains addresses for all memory locations having executable code and/or data. The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore!(R) is 4KB (4096 bytes). The Register File is composed of two sections--control registers and general-purpose registers. When instructions are executed, registers are read from when defined as sources and written to when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256-byte control register section are reserved (unavailable). Reading from an reserved Register File addresses returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The Z8F082x, Z8F081x, Z8F042x, and Z8F041x contain 1KB of on-chip RAM. Reading from Register File addresses outside the available RAM addresses (and not within the control register address space) returns an undefined value. Writing to these Register File addresses produces no effect.
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Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. The Z8F082x, Z8F081x, Z8F042x, and Z8F041x contain 4KB to 8KB of on-chip Flash memory in the Program Memory address space, depending upon the device. Reading from Program Memory addresses outside the available Flash memory addresses returns FFH. Writing to these unimplemented Program Memory addresses produces no effect. Table 5 describes the Program Memory Maps for the Z8F082x family products.
Table 5. Z8F082x Family Program Memory Maps Program Memory Address (Hex) Z8F082x and Z8F081x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-1FFF Z8F042x and Z8F041x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-0FFF Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Function
* See Table 23 on page 49 for a list of the interrupt vectors.
Data Memory
The Z8F082x family does not use the eZ8 CPU's 64KB Data Memory address space.
Flash Information Area
Table 6 describes the Z8F082x family Flash Information Area. This 512 byte Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When access is enabled, the Flash Information Area is mapped into the Program Memory and overlays the 512 bytes at addresses FE00H to FFFFH. When the Information Area access is enabled,
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all reads from these Program Memory addresses return the Information Area data rather than the Program Memory data. Acces to the Flash Information Area is read-only.
Table 6. Z8F082x Family Information Area Map Program Memory Address (Hex) FE00H-FE3FH FE40H-FE53H Function Reserved Part Number 20-character ASCII alphanumeric code Left justified and filled with zeros Reserved
FE54H-FFFFH
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Register File Address Map
Table 7 provides the address map for the Register File of the Z8F082x family of products. Not all devices and package styles in the Z8F082x family support the ADC, the SPI, or all of the GPIO Ports. Consider registers for unimplemented peripherals as Reserved.
Table 7. Register File Address Map Address (Hex) Register Description Mnemonic -- -- T0H T0L T0RH T0RL T0PWMH T0PWML T0CTL0 T0CTL1 T1H T1L T1RH T1RL T1PWMH T1PWML T1CTL0 T1CTL1 -- U0TXD U0RXD U0STAT0 U0CTL0 U0CTL1 U0STAT1 Reset (Hex) XX XX 00 01 FF FF 00 00 00 00 00 01 FF FF 00 00 00 00 XX XX XX 0000011Xb 00 00 00 69 69 70 70 72 72 73 73 69 69 70 70 72 72 73 73 Page # General Purpose RAM 000-3FF General-Purpose Register File RAM 400-EFF Reserved Timer 0 F00 F01 F02 F03 F04 F05 F06 F07 Timer 1 F08 F09 F0A F0B F0C F0D F0E F0F F10-F3F UART 0 F40 F41 F42 F43 F44 XX=Undefined Timer 0 High Byte Timer 0 Low Byte Timer 0 Reload High Byte Timer 0 Reload Low Byte Timer 0 PWM High Byte Timer 0 PWM Low Byte Timer 0 Control 0 Timer 0 Control 1 Timer 1 High Byte Timer 1 Low Byte Timer 1 Reload High Byte Timer 1 Reload Low Byte Timer 1 PWM High Byte Timer 1 PWM Low Byte Timer 1 Control 0 Timer 1 Control 1 Reserved UART0 Transmit Data UART0 Receive Data UART0 Status 0 UART0 Control 0 UART0 Control 1 UART0 Status 1
92 93 93 95 95 93
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Table 7. Register File Address Map (Continued) Address (Hex) F45 F46 F47 F48-F4F I2C F50 F51 F52 F53 F54 F55 F56 F57-F5F Register Description UART0 Address Compare Register UART0 Baud Rate High Byte UART0 Baud Rate Low Byte Reserved I2C Data I2C Status I2C Control I2C Baud Rate High Byte I2C Baud Rate Low Byte I2C Diagnostic State I2C Diagnostic Control Reserved Mnemonic U0ADDR U0BRH U0BRL -- I2CDATA I2CSTAT I2CCTL I2CBRH I2CBRL I2CDST I2CDIAG -- Reset (Hex) 00 FF FF XX 00 80 00 FF FF XX000000b 00 XX 01 00 00 00 00 XX FF FF XX 20 XX XX XX XX 00 00 00 00 00 00 00 00 00 XX Page # 98 99 99
127 128 129 130 130 132 132
Serial Peripheral Interface (SPI) Unavailable in 20-Pin Package Devices F60 SPI Data SPIDATA F61 SPI Control SPICTL F62 SPI Status SPISTAT F63 SPI Mode SPIMODE F64 SPI Diagnostic State SPIDST F65 Reserved -- F66 SPI Baud Rate High Byte SPIBRH F67 SPI Baud Rate Low Byte SPIBRL F68-F6F Reserved -- Analog-to-Digital Converter (ADC) F70 ADC Control F71 Reserved F72 ADC Data High Byte F73 ADC Data Low Bits F74-FBF Reserved Interrupt Controller FC0 Interrupt Request 0 FC1 IRQ0 Enable High Bit FC2 IRQ0 Enable Low Bit FC3 Interrupt Request 1 FC4 IRQ1 Enable High Bit FC5 IRQ1 Enable Low Bit FC6 Interrupt Request 2 FC7 IRQ2 Enable High Bit FC8 IRQ2 Enable Low Bit FC9-FCC Reserved XX=Undefined ADCCTL -- ADCDH ADCDL -- IRQ0 IRQ0ENH IRQ0ENL IRQ1 IRQ1ENH IRQ1ENL IRQ2 IRQ2ENH IRQ2ENL --
114 115 116 118 119 120 120
136 137 138
52 55 55 53 56 56 54 57 57
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Table 7. Register File Address Map (Continued) Address (Hex) FCD FCE FCF GPIO Port A FD0 FD1 FD2 FD3 GPIO Port B FD4 FD5 FD6 FD7 GPIO Port C FD8 FD9 FDA FDB FDC-FEF Register Description Interrupt Edge Select Reserved Interrupt Control Port A Address Port A Control Port A Input Data Port A Output Data Port B Address Port B Control Port B Input Data Port B Output Data Port C Address Port C Control Port C Input Data Port C Output Data Reserved Mnemonic IRQES -- IRQCTL PAADDR PACTL PAIN PAOUT PBADDR PBCTL PBIN PBOUT PCADDR PCCTL PCIN PCOUT -- WDTCTL WDTU WDTH WDTL -- FCTL FSTAT FPS FPROT FFREQH FFREQL Reset (Hex) 00 00 00 00 00 XX 00 00 00 XX 00 00 00 XX 00 XX XXX00000b FF FF FF XX 00 00 00 00 00 00 Page # 58 59 40 41 46 47 40 41 46 47 40 41 46 47
Watch-Dog Timer (WDT) FF0 Watch-Dog Timer Control FF1 Watch-Dog Timer Reload Upper Byte FF2 Watch-Dog Timer Reload High Byte FF3 Watch-Dog Timer Reload Low Byte FF4-FF7 Reserved Flash Memory Controller FF8 Flash Control FF8 Flash Status FF9 Flash Page Select FF9 (if enabled) Flash Sector Protect FFA Flash Programming Frequency High Byte FFB Flash Programming Frequency Low Byte Read-Only Memory eZ8 CPU FFC FFD FFE FFF XX=Undefined Flags Register Pointer Stack Pointer High Byte Stack Pointer Low Byte
78 80 80 80
145 146 147 148 149 149
-- RP SPH SPL
XX XX XX XX
Refer to the eZ8 CPU User Manual
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Preliminary
Register File Address Map
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
19
Contol Register Summary
Timer 0 High Byte T0H (%F00 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [15:8]
Timer 0 Control 1 T0CTL1 (%F07 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = Continuous mode 010 = Counter mode 011 = PWM mode 100 = Capture mode 101 = Compare mode 110 = Gated mode 111 = Capture/Compare mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled
Timer 0 Low Byte T0L (%F01 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [7:0]
Timer 0 Reload High Byte T0RH (%F02 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [15:8]
Timer 0 Reload Low Byte T0RL (%F03 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [7:0]
Timer 1 High Byte T1H (%F08 - Read/Write) Timer 0 PWM High Byte T0PWMH (%F04 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 PWM value [15:8] D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [15:8]
Timer 1 Low Byte T1L (%F09 - Read/Write) Timer 0 Control 0 T0CTL0 (%F06 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 0 Input signal is GPIO pin 1 = Timer 0 Input signal is Timer 1 out Reserved D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [7:0]
Timer 1 Reload High Byte T1RH (%F0A - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [15:8]
Timer 1 Reload Low Byte T1RL (%F0B - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [7:0]
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
20
Timer 1 PWM High Byte T1PWMH (%F0C - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [15:8]
UART0 Transmit Data U0TXD (%F40 - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 transmitter data byte [7:0]
Timer 1 PWM Low Byte T1PWML (%F0D - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [7:0]
UART0 Receive Data U0RXD (%F40 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 receiver data byte [7:0]
Timer 1 Control 0 T1CTL0 (%F0E - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 1 Input signal is GPIO pin 1 = Timer 1 Input signal is Timer 0 out Reserved
UART0 Status 0 U0STAT0 (%F41 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register
Timer 1 Control 1 T1CTL1 (%F0F - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = Continuous mode 010 = Counter mode 011 = PWM mode 100 = Capture mode 101 = Compare mode 110 = Gated mode 111 = Capture/Compare mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
21
UART0 Control 0 U0CTL0 (%F42 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled
UART0 Control 1 U0CTL1 (%F43 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match
UART0 Status 1 U0STAT1 (%F44- Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved
UART0 Address Compare U0ADDR (%F45 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 Address Compare [7:0]
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
22
UART0 Baud Rate Generator High Byte U0BRH (%F46 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [15:8]
I2C Control I2CCTL (%F52 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C Signal Filter Enable 0 = Digital filtering disabled 1 = Low-pass digital filters enabled on SDA and SCL input signals Flush Data 0 = No effect 1 = Clears I2C Data register Send NAK 0 = Do not send NAK 1 = Send NAK after next byte received from slave Enable TDRE Interrupts 0 = Do not generate an interrupt when the I2C Data register is empty 1 = Generate an interrupt when the I2C Transmit Data register is empty Baud Rate Generator Interrupt Request 0 = Interrupts behave as set by I2C control 1 = BRG generates an interrupt when it counts down to zero Send Stop Condition 0 = Do not issue Stop condition after data transmission is complete 1 = Issue Stop condition after data transmission is complete Send Start Condition 0 = Do not send Start Condition 1 = Send Start Condition I2C Enable 0 = I2C is disabled 1 = I2C is enabled
UART0 Baud Rate Generator Low Byte U0BRL (%F47 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [7:0]
I2C Data I2CDATA (%F50 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C data [7:0]
I2C Status I2CSTAT (%F51 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 NACK Interrupt 0 = No action required to service NAK 1 = START/STOP not set after NAK Data Shift State 0 = Data is not being transferred 1 = Data is being transferred Transmit Address State 0 = Address is not being transferred 1 = Address is being transferred Read 0 = Write operation 1 = Read operation 10-Bit Address 0 = 7-bit address being transmitted 1 = 10-bit address being transmitted Acknowledge 0 = Acknowledge not transmitted/received 1 = For last byte, Acknowledge was transmitted/received Receive Data Register Full 0 = I2C has not received data 1 = Data register contains received data Transmit Data Register Empty 0 = Data register is full 1 = Data register is empty
I2C Baud Rate Generator High Byte I2CBRH (%F53 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [15:8]
I2C Baud Rate Generator Low Byte I2CBRL (%F54 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [7:0]
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
23
SPI Data SPIDATA (%F60 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Data [7:0]
SPI Status SPISTAT (%F62 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Slave Select 0 = If Slave, SS pin is asserted 1 = If Slave, SS pin is not asserted Transmit Status 0 = No data transmission in progress 1 = Data transmission now in progress Reserved Slave Mode Transaction Abort 0 = No slave mode transaction abort detected 1 = Slave mode transaction abort was detected Collision 0 = No multi-master collision detected 1 = Multi-master collision was detected Overrun 0 = No overrun error detected 1 = Overrun error was detected Interrupt Request 0 = No SPI interrupt request pending 1 = SPI interrupt request is pending
SPI Control SPICTL (%F61 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Enable 0 = SPI disabled 1 = SPI enabled Master Mode Enabled 0 = SPI configured in Slave mode 1 = SPI configured in Master mode Wire-OR (open-drain) Mode Enabled 0 = SPI signals not configured for open-drain 1 = SPI signals (SCK, SS, MISO, and MOSI) configured for open-drain Clock Polarity 0 = SCK idles Low 1 = SPI idles High Phase Select Sets the phase relationship of the data to the clock. BRG Timer Interrupt Request 0 = BRG timer function is disabled 1 = BRG time-out interrupt is enabled Start an SPI Interrupt Request 0 = No effect 1 = Generate an SPI interrupt request Interrupt Request Enable 0 = SPI interrupt requests are disabled 1 = SPI interrupt requests are enabled
SPI Mode SPIMODE (%F63 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Slave Select Value If Master and SPIMODE[1] = 1: 0 = SS pin driven Low 1 = SS pin driven High Slave Select I/O 0 = SS pin configured as an input 1 = SS pin configured as an output (Master mode only) Number of Data Bits Per Character 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits 111 = 7 bits Diagnostic Mode Control 0 = Reading from SPIBRH, SPIBRL returns reload values 1 = Reading from SPIBRH, SPIBRL returns current BRG count value Reserved
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
24
SPI Diagnostic State SPIDST (%F64 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 SPI State Transmit Clock Enable 0 = Internal transmit clock enable signal is deasserted 1 = Internal transmit clock enable signal is asserted Shift Clock Enable 0 = Internal shift clock enable signal is deasserted 1 = Internal shift clock enable signal is asserted
ADC Data High Byte ADCD_H (%F72 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 ADC Data [9:2]
ADC Data Low Bits ADCD_L (%F73 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved ADC Data [1:0]
SPI Baud Rate Generator High Byte SPIBRH (%F66 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [15:8]
Interrupt Request 0 IRQ0 (%FC0 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC Interrupt Request SPI Interrupt Request I2C Interrupt Request
SPI Baud Rate Generator Low Byte SPIBRL (%F67 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [7:0]
UART 0 Transmitter Interrupt Request UART 0 Receiver Interrupt Request Timer 0 Interrupt Request Timer 1 Interrupt Request
ADC Control ADCCTL (%F70 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Analog Input Select 0000 = ANA0 0001 = ANA1 0010 = ANA2 0011 = ANA3 0100 = ANA4 0101 through 21111 = Reserved Continuous Mode Select 0 = Single-shot conversion 1 = Continuous conversion External VREF select 0 = Internal voltage reference selected 1 = External voltage reference selected Reserved Conversion Enable 0 = Conversion is complete 1 = Begin conversion
Reserved For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service
IRQ0 Enable High Bit IRQ0ENH (%FC1 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable High Bit I2C IRQ Enable High Bit UART 0 Transmitter IRQ Enable High UART 0 Receiver IRQ Enable High Bit Timer 0 IRQ Enable High Bit Timer 1 IRQ Enable High Bit Reserved
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
25
IRQ0 Enable Low Bit IRQ0ENL (%FC2 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable Low Bit I2C IRQ Enable Low Bit UART 0 Transmitter IRQ Enable Low UART 0 Receiver IRQ Enable Low Bit Timer 0 IRQ Enable Low Bit Timer 1 IRQ Enable Low Bit Reserved
IRQ2 Enable High Bit IRQ2ENH (%FC7 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable High Bit Reserved
IRQ2 Enable Low Bit IRQ2ENH (%FC8 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable Low Bit Reserved
Interrupt Request 1 IRQ1 (%FC3 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Pin Interrupt Request 0 = IRQ from corresponding pin [7:0] is not pending 1 = IRQ from corresponding pin [7:0] is awaiting service
Interrupt Control IRQES (%FCD - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Interrupt Request Enable 0 = Interrupts are disabled 1 = Interrupts are enabled
IRQ1 Enable High Bit IRQ1ENH (%FC4 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Pin IRQ Enable High Bit
Port A Address PAADDR (%FD0 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H = Pull-up enable 07H-FFH = No function
IRQ1 Enable Low Bit IRQ1ENL (%FC5 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Pin IRQ Enable Low Bit
Interrupt Request 2 IRQ2 (%FC6 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin Interrupt Request 0 = IRQ from corresponding pin [3:0] is not pending 1 = IRQ from corresponding pin [3:0] is awaiting service Reserved
Port A Control PACTL (%FD1 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Control[7:0] Provides Access to Port Sub-Registers
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
26
Port A Input Data PAIN (%FD2 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Input Data [7:0]
Port C Address PCADDR (%FD8 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H = Pull-up enable 07H-FFH = No function
Port A Output Data PAOUT (%FD3 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Output Data [7:0]
Port B Address PBADDR (%FD4 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H = Pull-up enable 07H-FFH = No function
Port C Control PCCTL (%FD9 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Control [5:0] Provides Access to Port Sub-Registers Reserved
Port C Input Data PCIN (%FDA - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Input Data [5:0]
Port B Control PBCTL (%FD5 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Control [4:0] Provides Access to Port Sub-Registers Reserved
Reserved
Port C Output Data PCOUT (%FDB - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Output Data [5:0]
Port B Input Data PBIN (%FD6 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Input Data [4:0] Reserved
Reserved
Port B Output Data PBOUT (%FD7 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Output Data [4:0] Reserved
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
27
Watch-Dog Timer Control WDTCTL (%FF0 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved EXT 0 = Reset not generated by RESET pin 1 = Reset generated by RESET pin WDT 0 = WDT timeout has not occurred 1 = WDT timeout occurred STOP 0 = SMR has not occurred 1 = SMR has occurred POR 0 = POR has not occurred 1 = POR has occurred
Flash Status FSTAT (%FF8 - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Controller Status 00_0000 = Flash controller locked 00_0001 = First unlock received 00_0010 = Second unlock received 00_0011 = Flash controller unlocked 00_0100 = Flash Sector Protect register selected 00_1xxx = Programming in progress 01_0xxx = Page erase in progress 10_0xxx = Mass erase in progress Reserved
Flash Page Select FPS (%FF9 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Page Select [6:0] Identifies the Flash memory page for Page Erase operation. Information Area Enable
Watch-Dog Timer Reload Upper Byte WDTU (%FF1 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [23:16]
Watch-Dog Timer Reload Middle Byte WDTH (%FF2 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [15:8]
Flash Sector Protect FPROT (%FF9 - Read/Write to 1's)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Sector Protect [7:0] 0 = Sector can be programmed or erased from user code 1 = Sector is protected and cannot be programmed or erased from user code
Watch-Dog Timer Reload Low Byte WDTL (%FF3 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [7:0]
Flash Frequency High Byte FFREQH (%FFA - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [15:8]
Flash Control FCTL (%FF8 - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Command 73H = First unlock command 8CH = Second unlock command 95H = Page erase command 63H = Mass erase command 5EH = Flash Sector Protect reg select
Flash Frequency Low Byte FFREQL (%FFB - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [7:0]
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
28
Flags FLAGS (%FFC - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 F1 - User Flag 1 F2 - User Flag 2 H - Half Carry D - Decimal Adjust V - Overflow Flag S - Sign Flag Z - Zero Flag C - Carry Flag
Register Pointer RP (%FFD - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Working Register Page Address [11:8] Working Register Group Address [7:4]
Stack Pointer High Byte SPH (%FFE - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [15:8]
Stack Pointer Low Byte SPL (%FFF - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [7:0]
PS019707-1003
Preliminary
Contol Register Summary
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
29
Reset and STOP Mode Recovery
Overview
The Reset Controller within the Z8F082x family controls Reset and STOP Mode Recovery operation. In typical operation, the following events cause a Reset to occur:
* * * * *
Power-On Reset (POR) Voltage Brown-Out (VBO) Watch-Dog Timer time-out (when configured via the WDT_RES Option Bit to initiate a Reset) External RESET pin assertion On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the Z8F082x family device is in STOP mode, a STOP Mode Recovery is initiated by either of the following:
* * * Reset Types
Watch-Dog Timer time-out GPIO Port input pin transition on an enabled STOP Mode Recovery source DBG pin driven Low
The Z8F082x family provides two different types of reset operation (System Reset and STOP Mode Recovery). The type of Reset is a function of both the current operating mode of the Z8F082x family device and the source of the Reset. Table 7 lists the types of Reset and their operating characteristics.
Table 7. Reset and STOP Mode Recovery Characteristics and Latency Reset Characteristics and Latency Reset Type System Reset STOP Mode Recovery Control Registers Reset (as applicable) Unaffected, except WDT_CTL register eZ8 CPU Reset Latency (Delay) Reset Reset 66 WDT Oscillator cycles + 16 System Clock cycles 66 WDT Oscillator cycles + 16 System Clock cycles
PS019707-1003
Preliminary
Reset and STOP Mode Recovery
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
30
System Reset
During a System Reset, the Z8F082x family device is held in Reset for 66 cycles of the Watch-Dog Timer oscillator followed by 16 cycles of the system clock. At the beginning of Reset, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are disabled. During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal oscillator and Watch-Dog Timer oscillator continue to run. The system clock begins operating following the Watch-Dog Timer oscillator cycle count. The eZ8 CPU and on-chip peripherals remain idle through the 16 cycles of the system clock. Upon Reset, control registers within the Register File that have a defined Reset value are loaded with their reset values. Other control registers (including the Stack Pointer, Register Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address.
Reset Sources
Table 8 lists the reset sources as a function of the operating mode. The text following provides more detailed information on the individual Reset sources. Please note that a PowerOn Reset / Voltage Brown-Out event always has priority over all other possible reset sources to insure a full system reset occurs.
Table 8. Reset Sources and Resulting Reset Type Operating Mode Normal or HALT modes Reset Source Reset Type
Power-On Reset / Voltage Brown-Out System Reset Watch-Dog Timer time-out when configured for Reset RESET pin assertion On-Chip Debugger initiated Reset (OCDCTL[0] set to 1) System Reset System Reset System Reset except the On-Chip Debugger is unaffected by the reset
STOP mode
Power-On Reset / Voltage Brown-Out System Reset RESET pin assertion DBG pin driven Low System Reset System Reset
Power-On Reset
Each device in the Z8F082x family contains an internal Power-On Reset (POR) circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until
PS019707-1003
Preliminary
Reset and STOP Mode Recovery
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
31
the supply voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the Watch-Dog Timer oscillator. After the POR counter times out, the XTAL Counter is enabled to count a total of 16 system clock pulses. The device is held in the Reset state until both the POR Counter and XTAL counter have timed out. After the Z8F082x family device exits the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1. Figure 6 illustrates Power-On Reset operation. Refer to the Electrical Characteristics chapter for the POR threshold voltage (VPOR).
VCC = 3.3V VPOR VVBO
VCC = 0.0V
Program Execution
WDT Clock
Primary Oscillator Oscillator Start-up
Internal RESET signal
Not to Scale
WDT osc counter delay
XTAL counter delay
Figure 6. Power-On Reset Operation)
Voltage Brown-Out Reset
The devices in the Z8F082x family provide low Voltage Brown-Out (VBO) protection. The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO block holds the device in the Reset state.
PS019707-1003
Preliminary
Reset and STOP Mode Recovery
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
32
After the supply voltage again exceeds the Power-On Reset voltage threshold, the device progresses through a full System Reset sequence, as described in the Power-On Reset section. Following Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1. Figure 7 illustrates Voltage Brown-Out operation. Refer to the Electrical Characteristics chapter for the VBO and POR threshold voltages (VVBO and VPOR). The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode. Operation during STOP mode is set by the VBO_AO Option Bit. Refer to the Option Bits chapter for information on configuring VBO_AO.
VCC = 3.3V VPOR VVBO
Program Execution Voltage Brownout Program Execution
VCC = 3.3V
WDT Clock Primary Oscillator
Internal RESET signal
WDT counter delay
Figure 7. Voltage Brown-Out Reset Operation
XTAL counter delay
Watch-Dog Timer Reset
If the device is in normal or HALT mode, the Watch-Dog Timer can initiate a System Reset at time-out if the WDT_RES Option Bit is set to 1. This is the default (unprogrammed) setting of the WDT_RES Option Bit. The WDT status bit in the WDT Control register is set to signify that the reset was initiated by the Watch-Dog Timer.
PS019707-1003
Preliminary
Reset and STOP Mode Recovery
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
33
External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, and a digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock cycles, the device progresses through the System Reset sequence. While the RESET input pin is asserted Low, the Z8F082x family device continues to be held in the Reset state. If the RESET pin is held Low beyond the System Reset time-out, the device exits the Reset state immediately following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1.
STOP Mode Recovery
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the Low-Power Modes chapter for detailed STOP mode information. During STOP Mode Recovery, the device is held in reset for 66 cycles of the Watch-Dog Timer oscillator followed by 16 cycles of the system clock. STOP Mode Recovery only affects the contents of the Watch-Dog Timer Control register. Stop Mode recovery does not affect any other values in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral control registers, and general-purpose RAM. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address. Following STOP Mode Recovery, the STOP bit in the Watch-Dog Timer Control Register is set to 1. Table 9 lists the STOP Mode Recovery sources and resulting actions. The text following provides more detailed information on each of the STOP Mode Recovery sources.
Table 9. STOP Mode Recovery Sources and Resulting Action Operating Mode STOP mode STOP Mode Recovery Source Watch-Dog Timer time-out when configured for Reset Watch-Dog Timer time-out when configured for interrupt Data transition on any GPIO Port pin enabled as a STOP Mode Recovery source Action STOP Mode Recovery STOP Mode Recovery followed by interrupt (if interrupts are enabled) STOP Mode Recovery
STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP Mode Recovery sequence. In the Watch-Dog Timer Control register, the WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon time-
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out and the Z8F082x family device is configured to respond to interrupts, the eZ8 CPU services the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source. On any GPIO pin enabled as a Stop Mode Recover source, a change in the input pin value (from High to Low or from Low to High) initiates STOP Mode Recovery. The GPIO STOP Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in duration. In the Watch-Dog Timer Control register, the STOP bit is set to 1. Caution: In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input Data registers record the Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay. Thus, short pulses on the Port pin can initiate STOP Mode Recovery without being written to the Port Input Data register or without initiating an interrupt (if enabled for that pin).
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Low-Power Modes
Overview
The Z8F082x family products contain power-saving features. The highest level of power reduction is provided by STOP mode. The next level of power reduction is provided by the HALT mode.
STOP Mode
Execution of the eZ8 CPU's STOP instruction places the device into STOP mode. In STOP mode, the operating characteristics are:
* * * * * * *
Primary crystal oscillator is stopped; XIN and XOUT pins are driven Low. System clock is stopped eZ8 CPU is stopped Program counter (PC) stops incrementing If enabled for operation in Stop Mode, the Watch-Dog Timer and its internal RC oscillator continue to operate If enabled for operation in STOP mode via the associated Option Bit, the Voltagebrown out protection circuit continues to operate All other on-chip peripherals are idle
To minimize current in STOP mode, the Watch-Dog Timer should be disabled and all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND). The device can be brought out of STOP mode using STOP Mode Recovery. For more information on STOP Mode Recovery refer to the Reset and STOP Mode Recovery chapter on page 29. Caution: STOP Mode should not be used when driving the Z8F082x family devices with an external clock driver source (since the XIN and XOUT pins are driven Low in STOP Mode).
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HALT Mode
Execution of the eZ8 CPU's HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are:
* * * * * * * * * * * *
Primary crystal oscillator is enabled and continues to operate System clock is enabled and continues to operate eZ8 CPU is stopped Program counter (PC) stops incrementing Watch-Dog Timer's internal RC oscillator continues to operate If enabled, the Watch-Dog Timer continues to operate All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations: Interrupt Watch-Dog Timer time-out (interrupt or reset) Power-on reset Voltage-brown out reset External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be driven to one of the supply rails (VCC or GND).
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General-Purpose I/O
Overview
The Z8F082x family products support a maximum of 19 port pins (Ports A-C) for general-purpose input/output (GPI/O) operations. Each port contains control and data registers. The GPIO control registers are used to determine data direction, open-drain, output drive current, programmable pull-ups, STOP Mode Recovery functionality, and alternate pin functions. Each port pin is individually programmable.
GPIO Port Availability By Device
Table 10 lists the port pins available with each device and package type.
Table 10. Port Availability by Device and Package Type Devices Z8F0821, Z8F0811, Z8F0421, Z8F0411 Z8F0822, Z8F0812, Z8F0422, Z8F0412 Package 20 pin 28 pin Port A [7:0] [7:0] Port B [1:0] [4:0] Port C [0] [5:0]
Architecture
Figure 8 illustrates a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions, variable port current drive strength, and programmable pull-up are not illustrated.
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Port Input Data Register Q D Q D
Schmitt Trigger
System Clock VDD Port Output Control Port Output Data Register DATA Bus System Clock D Q Port Pin
Port Data Direction GND
Figure 8. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access to on-chip peripheral functions such as the timers and serial communication devices. The Port A-C Alternate Function sub-registers configure these pins for either general-purpose I/O or alternate function operation. When a pin is configured for alternate function, control of the port pin direction (input/output) is passed from the Port A-C Data Direction registers to the alternate function assigned to this pin. Table 11 lists the alternate functions associated with each port pin.
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Table 11. Port Alternate Function Mapping Port Port A Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Port B PB0 PB1 PB2 PB3 PB4 Port C PC0 PC1 PC2 PC3 PC4 PC5 Mnemonic T0IN T0OUT DE CTS0 Alternate Function Description Timer 0 Input Timer 0 Output UART 0 Driver Enable UART 0 Clear to Send
RXD0 / IRRX0 UART 0 / IrDA 0 Receive Data TXD0 / IRTX0 SCL SDA ANA0 ANA1 ANA2 ANA3 ANA4 T1IN T1OUT SS SCK MOSI MISO UART 0 / IrDA 0 Transmit Data I2C Clock (automatically open-drain) I2C Data (automatically open-drain) ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 Timer 1 Input Timer 1 Output SPI Slave Select SPI Serial Clock SPI Master Out Slave In SPI Master In Slave Out
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other port pin interrupts generate an interrupt when any edge occurs (both rising and falling). Refer to the Interrupt Controller chapter for more information on interrupts using the GPIO pins.
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GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data. Table 12 lists these Port registers. Use the Port A-C Address and Control registers together to provide access to sub-registers for Port configuration and control.
Table 12. GPIO Port Registers and Sub-Registers Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Sub-Register Mnemonic PxDD PxAF PxOC PxHDE PxSMRE PxPUE Port Register Name Port A-C Address Register (Selects sub-registers) Port A-C Control Register (Provides access to sub-registers) Port A-C Input Data Register Port A-C Output Data Register Port Register Name Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable Pull-up Enable
Port A-C Address Registers
The Port A-C Address registers select the GPIO Port functionality accessible through the Port A-C Control registers. The Port A-C Address and Control registers combine to provide access to all GPIO Port control (Table 13).
Table 13. Port A-C GPIO Address Registers (PxADDR)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
PADDR[7:0] 00H R/W FD0H, FD4H, FD8H
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PADDR[7:0]--Port Address The Port Address selects one of the sub-registers accessible through the Port Control register.
PADDR[7:0] 00H 01H 02H 03H 04H 05H 06H 07H-FFH Port Control sub-register accessible using the Port A-C Control Registers No function. Provides some protection against accidental Port reconfiguration. Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable. Pull-up Enable No function.
Port A-C Control Registers
The Port A-C Control registers set the GPIO port operation. The value in the corresponding Port A-C Address register determines the control sub-registers accessible using the Port A-C Control register (Table 14).
Table 14. Port A-C Control Registers (PxCTL)
BITS FIELD RESET R/W ADDR
7
6
5
4
PCTL 00H R/W
3
2
1
0
FD1H, FD5H, FD9H
PCTL[7:0]--Port Control The Port Control register provides access to all sub-registers that configure the GPIO Port operation.
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Port A-C Data Direction Sub-Registers The Port A-C Data Direction sub-register is accessed through the Port A-C Control register by writing 01H to the Port A-C Address register (Table 15).
Table 15. Port A-C Data Direction Sub-Registers
BITS FIELD RESET R/W ADDR
7
DD7 1 R/W
6
DD6 1 R/W
5
DD5 1 R/W
4
DD4 1 R/W
3
DD3 1 R/W
2
DD2 1 R/W
1
DD1 1 R/W
0
DD0 1 R/W
If 01H in Port A-C Address Register, accessible via Port A-C Control Register
DD[7:0]--Data Direction These bits control the direction of the associated port pin. Port Alternate Function operation overrides the Data Direction register setting. 0 = Output. Data in the Port A-C Output Data register is driven onto the port pin. 1 = Input. The port pin is sampled and the value written into the Port A-C Input Data Register. The output driver is tri-stated. Port A-C Alternate Function Sub-Registers The Port A-C Alternate Function sub-register (Table 16) is accessed through the Port A-C Control register by writing 02H to the Port A-C Address register. The Port A-C Alternate Function sub-registers select the alternate functions for the selected pins. Refer to the GPIO Alternate Functions section to determine the alternate function associated with each port pin. Caution: Do not enable alternate function for GPIO port pins which do not have an associated alternate function. Failure to follow this guideline may result in unpredictable operation.
Table 16. Port A-C Alternate Function Sub-Registers
BITS FIELD RESET R/W ADDR
7
AF7 0 R/W
6
AF6 0 R/W
5
AF5 0 R/W
4
AF4 0 R/W
3
AF3 0 R/W
2
AF2 0 R/W
1
AF1 0 R/W
0
AF0 0 R/W
If 02H in Port A-C Address Register, accessible via Port A-C Control Register
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AF[7:0]--Port Alternate Function enabled 0 = The port pin is in NORMAL mode and the DDx bit in the Port A-C Data Direction sub-register determines the direction of the pin. 1 = The alternate function is selected. Port pin operation is controlled by the alternate function. Port A-C Output Control Sub-Registers The Port A-C Output Control sub-register (Table 17) is accessed through the Port A-C Control register by writing 03H to the Port A-C Address register. Setting the bits in the Port A-C Output Control sub-registers to 1 configures the specified port pins for opendrain operation. These sub-registers affect the pins directly and, as a result, alternate functions are also affected.
Table 17. Port A-C Output Control Sub-Registers
BITS FIELD RESET R/W ADDR
7
POC7 0 R/W
6
POC6 0 R/W
5
POC5 0 R/W
4
POC4 0 R/W
3
POC3 0 R/W
2
POC2 0 R/W
1
POC1 0 R/W
0
POC0 0 R/W
If 03H in Port A-C Address Register, accessible via Port A-C Control Register
POC[7:0]--Port Output Control These bits function independently of the alternate function bit and always disable the drains if set to 1. 0 = The drains are enabled for any output mode (unless overridden by the alternate function). 1 = The drain of the associated pin is disabled (open-drain mode).
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Port A-C High Drive Enable Sub-Registers The Port A-C High Drive Enable sub-register (Table 18) is accessed through the Port A-C Control register by writing 04H to the Port A-C Address register. Setting the bits in the Port A-C High Drive Enable sub-registers to 1 configures the specified port pins for high current output drive operation. The Port A-C High Drive Enable sub-register affects the pins directly and, as a result, alternate functions are also affected.
Table 18. Port A-C High Drive Enable Sub-Registers
BITS FIELD RESET R/W ADDR
7
PHDE7 0 R/W
6
PHDE6 0 R/W
5
PHDE5 0 R/W
4
PHDE4 0 R/W
3
PHDE3 0 R/W
2
PHDE2 0 R/W
1
PHDE1 0 R/W
0
PHDE0 0 R/W
If 04H in Port A-C Address Register, accessible via Port A-C Control Register
PHDE[7:0]--Port High Drive Enabled 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. Port A-C STOP Mode Recovery Source Enable Sub-Registers The Port A-C STOP Mode Recovery Source Enable sub-register (Table 19) is accessed through the Port A-C Control register by writing 05H to the Port A-C Address register. Setting the bits in the Port A-C STOP Mode Recovery Source Enable sub-registers to 1 configures the specified Port pins as a STOP Mode Recovery source. During Stop Mode, any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates STOP Mode Recovery.
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Table 19. Port A-C STOP Mode Recovery Source Enable Sub-Registers
BITS FIELD RESET R/W ADDR
7
PSMRE7 0 R/W
6
PSMRE6 0 R/W
5
PSMRE5 0 R/W
4
PSMRE4 0 R/W
3
PSMRE3 0 R/W
2
PSMRE2 0 R/W
1
PSMRE1 0 R/W
0
PSMRE0 0 R/W
If 05H in Port A-C Address Register, accessible via Port A-C Control Register
PSMRE[7:0]--Port STOP Mode Recovery Source Enabled 0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this pin during STOP mode do not initiate STOP Mode Recovery. 1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on this pin during STOP mode initiates STOP Mode Recovery. Port A-C Pull-up Enable Sub-Registers The Port A-C Pull-up Enable sub-register (Table 20) is accessed through the Port A-C Control register by writing 06H to the Port A-C Address register. Setting the bits in the Port A-C Pull-up Enable sub-registers enables a weak internal resistive pull-up on the specified Port pins.
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Table 20. Port A-C Pull-Up Enable Sub-Registers
BITS FIELD RESET R/W ADDR
7
PPUE7 0 R/W
6
PPUE6 0 R/W
5
PPUE5 0 R/W
4
PPUE4 0 R/W
3
PPUE3 0 R/W
2
PPUE2 0 R/W
1
PPUE1 0 R/W
0
PPUE0 0 R/W
If 06H in Port A-C Address Register, accessible via Port A-C Control Register
PPUE[7:0]--Port Pull-up Enabled 0 = The weak pull-up on the Port pin is disabled. 1 = The weak pull-up on the Port pin is enabled.
Port A-C Input Data Registers
Reading from the Port A-C Input Data registers (Table 21) returns the sampled values from the corresponding port pins. The Port A-C Input Data registers are Read-only.
Table 21. Port A-C Input Data Registers (PxIN)
BITS FIELD RESET R/W ADDR
7
PIN7 X R
6
PIN6 X R
5
PIN5 X R
4
PIN4 X R
3
PIN3 X R
2
PIN2 X R
1
PIN1 X R
0
PIN0 X R
FD2H, FD6H, FDAH
PIN[7:0]--Port Input Data Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High).
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Port A-C Output Data Register
The Port A-C Output Data register (Table 22) controls the output data to the pins.
Table 22. Port A-C Output Data Register (PxOUT)
BITS FIELD RESET R/W ADDR
7
POUT7 0 R/W
6
POUT6 0 R/W
5
POUT5 0 R/W
4
POUT4 0 R/W
3
POUT3 0 R/W
2
POUT2 0 R/W
1
POUT1 0 R/W
0
POUT0 0 R/W
FD3H, FD7H, FDBH
POUT[7:0]--Port Output Data These bits contain the data to be driven to the port pins. The values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = Drive a logical 0 (Low). 1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting the corresponding Port Output Control register bit to 1.
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Interrupt Controller
Overview
The interrupt controller on the Z8F082x family products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt controller include the following:
*
19 unique interrupt vectors: - 12 GPIO port pin interrupt sources - 7 on-chip peripheral interrupt sources Flexible GPIO interrupts - 8 selectable rising and falling edge GPIO interrupts - 4 dual-edge interrupts 3 levels of individually programmable interrupt priority Watch-Dog Timer can be configured to generate an interrupt
*
* *
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control information between the CPU and the interrupting peripheral. When the service routine is completed, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Manual is available for download at www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address.
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Table 23. Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt Source Highest 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0010h 0012h 0014h 0016h 0018h 001Ah 001Ch 001Eh 0020h 0022h 0024h 0026h 0028h 002Ah 002Ch 002Eh 0030h 0032h 0034h Lowest 0036h Reset (not an interrupt) Watch-Dog Timer (see the section Watch-Dog
Timer on page 75)
Illegal Instruction Trap (not an interrupt) Reserved Timer 1 Timer 0 UART 0 receiver UART 0 transmitter I2C SPI ADC Port A7, rising or falling input edge Port A6, rising or falling input edge Port A5, rising or falling input edge Port A4, rising or falling input edge Port A3, rising or falling input edge Port A2, rising or falling input edge Port A1, rising or falling input edge Port A0, rising or falling input edge Reserved Reserved Reserved Reserved Port C3, both input edges Port C2, both input edges Port C1, both input edges Port C0, both input edges
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Architecture
Figure 9 illustrates a block diagram of the interrupt controller.
Port Interrupts Interrupt Request Latches and Control
High Priority Vector Priority Mux IRQ Request
Medium Priority
Internal Interrupts
Low Priority
Figure 9. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions:
* * * * * * *
Execution of an EI (Enable Interrupt) instruction Execution of an IRET (Return from Interrupt) instruction Writing a 1 to the IRQE bit in the Interrupt Control register Execution of a DI (Disable Interrupt) instruction eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller Writing a 0 to the IRQE bit in the Interrupt Control register Reset
Interrupts are globally disabled by any of the following actions:
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* *
Execution of a Trap instruction Illegal Instruction trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for example), then interrupt priority would be assigned from highest to lowest as specified in Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23. Reset, Watch-Dog Timer interrupt (if enabled), and Illegal Instruction Trap always have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corresponding bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt request. Caution: The following style of coding to clear bits in the Interrupt Request registers is NOT recommended. All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 To avoid missing interrupts, the following style of coding to clear bits in the Interrupt Request 0 register is recommended: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the desired bit in the Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). When the interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is automatically cleared to 0.
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Caution:
The following style of coding to generate software interrupts by setting bits in the Interrupt Request registers is NOT recommended. All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0
Note:
To avoid missing interrupts, the following style of coding to set bits in the Interrupt Request registers is recommended: Good coding style that avoids lost interrupt requests: ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watch-Dog Timer interrupt, the interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 24) stores the interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending.
Table 24. Interrupt Request 0 Register (IRQ0)
BITS FIELD RESET R/W ADDR
7
Reserved 0 R/W
6
T1I 0 R/W
5
T0I 0 R/W
4
U0RXI 0 R/W FC0H
3
U0TXI 0 R/W
2
I2CI 0 R/W
1
SPII 0 R/W
0
ADCI 0 R/W
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Reserved--Must be 0. T1I--Timer 1 Interrupt Request 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. T0I--Timer 0 Interrupt Request 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service. U0RXI--UART 0 Receiver Interrupt Request 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. U0TXI--UART 0 Transmitter Interrupt Request 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. I2CI-- I2C Interrupt Request 0 = No interrupt request is pending for the I2C. 1 = An interrupt request from the I2C is awaiting service. SPII--SPI Interrupt Request 0 = No interrupt request is pending for the SPI. 1 = An interrupt request from the SPI is awaiting service. ADCI--ADC Interrupt Request 0 = No interrupt request is pending for the Analog-to-Digital Converter. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending.
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Table 25. Interrupt Request 1 Register (IRQ1)
BITS FIELD RESET R/W ADDR
7
PA7I 0 R/W
6
PA6I 0 R/W
5
PA5I 0 R/W
4
PA4I 0 R/W FC3H
3
PA3I 0 R/W
2
PA2I 0 R/W
1
PA1I 0 R/W
0
PA0I 0 R/W
PAxI--Port A Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port A pin x. 1 = An interrupt request from GPIO Port A pin x is awaiting service. where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 26) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2 register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 2 Register (IRQ2)
BITS FIELD RESET R/W ADDR
7
6
Reserved
5
4
3
PC3I
2
PC2I 0 R/W
1
PC1I 0 R/W
0
PC0I 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W FC6H
0 R/W
Reserved--Must be 0. PCxI--Port C Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. where x indicates the specific GPIO Port C pin number (0 through 3).
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IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (Tables 28 and Table 29) form a priority encoded enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting bits in each register. Table 27 describes the priority control for IRQ0.
Table 27. IRQ0 Enable and Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Nominal High
where x indicates the register bits from 0 through 7.
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS FIELD RESET R/W ADDR
7
Reserved 0 R/W
6
T1ENH 0 R/W
5
T0ENH 0 R/W
4
U0RENH 0 R/W FC1H
3
U0TENH 0 R/W
2
I2CENH 0 R/W
1
SPIENH 0 R/W
0
ADCENH 0 R/W
Reserved--Must be 0. T1ENH--Timer 1 Interrupt Request Enable High Bit T0ENH--Timer 0 Interrupt Request Enable High Bit U0RENH--UART 0 Receive Interrupt Request Enable High Bit U0TENH--UART 0 Transmit Interrupt Request Enable High Bit I2CENH--I2C Interrupt Request Enable High Bit SPIENH--SPI Interrupt Request Enable High Bit ADCENH--ADC Interrupt Request Enable High Bit
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Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS FIELD RESET R/W ADDR
7
Reserved 0 R/W
6
T1ENL 0 R/W
5
T0ENL 0 R/W
4
U0RENL 0 R/W FC2H
3
U0TENL 0 R/W
2
I2CENL 0 R/W
1
SPIENL 0 R/W
0
ADCENL 0 R/W
Reserved--Must be 0. T1ENL--Timer 1 Interrupt Request Enable Low Bit T0ENL--Timer 0 Interrupt Request Enable Low Bit U0RENL--UART 0 Receive Interrupt Request Enable Low Bit U0TENL--UART 0 Transmit Interrupt Request Enable Low Bit I2CENL--I2C Interrupt Request Enable Low Bit SPIENL--SPI Interrupt Request Enable Low Bit ADCENL--ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (Tables 31 and Table 32) form a priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting bits in each register. Table 30 describes the priority control for IRQ1.
Table 30. IRQ1 Enable and Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Nominal High
where x indicates the register bits from 0 through 7.
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Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS FIELD RESET R/W ADDR
7
PA7ENH 0 R/W
6
PA6ENH 0 R/W
5
PA5ENH 0 R/W
4
PA4ENH 0 R/W FC4H
3
PA3ENH 0 R/W
2
PA2ENH 0 R/W
1
PA1ENH 0 R/W
0
PA0ENH 0 R/W
PAxENH--Port A Bit[x] Interrupt Request Enable High Bit
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS FIELD RESET R/W ADDR
7
PA7ENL 0 R/W
6
PA6ENL 0 R/W
5
PA5ENL 0 R/W
4
PA4ENL 0 R/W FC5H
3
PA3ENL 0 R/W
2
PA2ENL 0 R/W
1
PA1ENL 0 R/W
0
PA0ENL 0 R/W
PAxENL--Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers (Tables 34 and Table 35) form a priority encoded enabling for interrupts in the Interrupt Request 2 register. Priority is generated by setting bits in each register. Table 33 describes the priority control for IRQ2.
Table 33. IRQ2 Enable and Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Nominal High
where x indicates the register bits from 0 through 7.
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Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS FIELD RESET R/W ADDR
7
6
Reserved
5
4
3
C3ENH
2
C2ENH 0 R/W
1
C1ENH 0 R/W
0
C0ENH 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W FC7H
0 R/W
Reserved--Must be 0. C3ENH--Port C3 Interrupt Request Enable High Bit C2ENH--Port C2 Interrupt Request Enable High Bit C1ENH--Port C1 Interrupt Request Enable High Bit C0ENH--Port C0 Interrupt Request Enable High Bit
Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS FIELD RESET R/W ADDR
7
6
Reserved
5
4
3
C3ENL
2
C2ENL 0 R/W
1
C1ENL 0 R/W
0
C0ENL 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W FC8H
0 R/W
Reserved--Must be 0. C3ENL--Port C3 Interrupt Request Enable Low Bit C2ENL--Port C2 Interrupt Request Enable Low Bit C1ENL--Port C1 Interrupt Request Enable Low Bit C0ENL--Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 36) determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port input pin. The min-
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imum pulse width must be greater than 1 system clock to guarantee capture of the edge triggered interrupt. Edge detection for pulses less than 1 system clock are not guaranteed.
Table 36. Interrupt Edge Select Register (IRQES)
BITS FIELD RESET R/W ADDR
7
IES7 0 R/W
6
IES6 0 R/W
5
IES5 0 R/W
4
IES4 0 R/W FCDH
3
IES3 0 R/W
2
IES2 0 R/W
1
IES1 0 R/W
0
IES0 0 R/W
IESx--Interrupt Edge Select x 0 = An interrupt request is generated on the falling edge of the PAx input. 1 = An interrupt request is generated on the rising edge of the PAx input. where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 37) contains the master enable bit for all interrupts.
Table 37. Interrupt Control Register (IRQCTL)
BITS FIELD RESET R/W ADDR
7
IRQE 0 R/W
6
5
4
3
Reserved
2
1
0
0 R
0 R
0 R FCFH
0 R
0 R
0 R
0 R
IRQE--Interrupt Request Enable This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return) instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct register write of a 0 to this bit. 0 = Interrupts are disabled. 1 = Interrupts are enabled. Reserved--Must be 0.
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Timers
Overview
These Z8F082x family products contain up to two 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The timers' features include:
* * * * * * *
16-bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. Timer output pin Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any unused UART, SPI, or I2C peripherals may also be used to provide basic timing functionality. Refer to the respective serial communication peripheral chapters for information on using the Baud Rate Generators as timers.
Architecture
Figure 10 illustrates the architecture of the timers.
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Timer Block Data Bus Block Control Timer Control
Compare
16-Bit Reload Register
System Clock Timer Input Gate Input Capture Input
Interrupt, PWM, and Timer Output Control
Timer Interrupt Timer Output
16-Bit Counter with Prescaler Compare
16-Bit PWM / Compare
Figure 10. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128. If the Timer reaches FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes: ONE-SHOT Mode In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and stops counting. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
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it is desired to have the Timer Output make a permanent state change upon One-Shot timeout, first set the TPOL bit in the Timer Control Register to the start value before beginning ONE-SHOT mode. Then, after starting the timer, set TPOL to the opposite bit value. The steps for configuring a timer for ONE-SHOT mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for ONE-SHOT mode. - Set the prescale value. - If using the Timer Output alternate function, set the initial output level (High or Low). 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer and initiate counting. In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: ( Reload Value - Start Value ) x Prescale ONE-SHOT Mode Time-Out Period (s) = ----------------------------------------------------------------------------------------------------System Clock Frequency (Hz) CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon timer Reload. The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CONTINUOUS mode. - Set the prescale value.
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-
If using the Timer Output alternate function, set the initial output level (High or Low).
2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H). This only affects the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer and initiate counting. In CONTINUOUS mode, the system clock always provides the timer input. The timer period is given by the following equation: Reload Value x Prescale CONTINUOUS Mode Time-Out Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation must be used to determine the first time-out period. COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled. Caution: The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COUNTER mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for COUNTER mode.
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Select either the rising edge or falling edge of the Timer Input signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function does not have to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value of 0001H. Generally, in COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control register to enable the timer. In COUNTER mode, the number of Timer Input transitions since the timer start is given by the following equation: COUNTER Mode Timer Input Transitions = Current Count Value - Start Value
PWM Mode In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as a High (1) and then transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as a Low (0) and then transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows:
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1. Write to the Timer Control register to: - Disable the timer - Configure the timer for PWM mode. - Set the prescale value. - Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. 5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control register to enable the timer and initiate counting. The PWM period is given by the following equation: Reload Value x Prescale PWM Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the One-Shot mode equation must be used to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by: Reload Value - PWM Value PWM Output High Time Ratio (%) = ----------------------------------------------------------------------- x 100 Reload Value If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by: PWM Value PWM Output High Time Ratio (%) = --------------------------------- x 100 Reload Value CAPTURE Mode In CAPTURE mode, the current timer count value is recorded when the desired external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the
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Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt and continues counting. The steps for configuring a timer for CAPTURE mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CAPTURE mode. - Set the prescale value. - Set the Capture edge (rising or falling) for the Timer Input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, then the interrupt was generated by a Reload. 5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Input alternate function. 7. Write to the Timer Control register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: ( Capture Value - Start Value ) x Prescale Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
COMPARE Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon Compare.
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If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. The steps for configuring a timer for COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for COMPARE mode. - Set the prescale value. - Set the initial logic level (High or Low) for the Timer Output alternate function, if desired. 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control register to enable the timer and initiate counting. In COMPARE mode, the system clock always provides the timer input. The Compare time is given by the following equation: ( Compare Value - Start Value ) x Prescale Compare Mode Time (s) = ----------------------------------------------------------------------------------------------------------System Clock Frequency (Hz) GATED Mode In GATED mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. The steps for configuring a timer for GATED mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer
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Configure the timer for GATED mode. Set the prescale value.
2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. Write to the Timer Control register to enable the timer. 7. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer Input transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control Register. The timer input is the system clock. Every subsequent desired transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte Registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control register to: - Disable the timer - Configure the timer for CAPTURE/COMPARE mode. - Set the prescale value. - Set the Capture edge (rising or falling) for the Timer Input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers.
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5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. Write to the Timer Control register to enable the timer. 7. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: ( Capture Value - Start Value ) x Prescale Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte register is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled every time the counter is reloaded.
Timer Control Register Definitions
Timer 0-1 High and Low Byte Registers
The Timer 0-1 High and Low Byte (TxH and TxL) registers (Tables 38 and 39) contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TMRL always returns this temporary register when the timers are enabled. When the timer is disabled, reads from the TMRL reads the register directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recommended. There are no temporary holding registers available for write operations, so simultaneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
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written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter continues counting from the new value.
Table 38. Timer 0-1 High Byte Register (TxH)
BITS FIELD RESET R/W ADDR
7
6
5
4
TH
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
F00H, F08H
Table 39. Timer 0-1 Low Byte Register (TxL)
BITS FIELD RESET R/W ADDR
7
6
5
4
TL
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
F01H, F09H
TH and TL--Timer High and Low Bytes These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-1 Reload High and Low Byte (TxRH and TxRL) registers (Tables 40 and 41) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte register are stored in a temporary holding register. When a write to the Timer Reload Low Byte register occurs, the temporary holding register value is written to the Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer Reload value.
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In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit Compare value.
Table 40. Timer 0-1 Reload High Byte Register (TxRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
TRH
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
F02H, F0AH
Table 41. Timer 0-1 Reload Low Byte Register (TxRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
TRL
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
F03H, F0BH
TRH and TRL--Timer Reload Register High and Low These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the maximum count value which initiates a timer reload to 0001H. In COMPARE mode, these two byte form the 16-bit Compare value.
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Timer 0-1 PWM High and Low Byte Registers
The Timer 0-1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Tables 42 and 43) are used for Pulse-Width Modulator (PWM) operations. These registers also store the Capture values for the CAPTURE and CAPTURE/COMPARE modes.
Table 42. Timer 0-1 PWM High Byte Register (TxPWMH)
BITS FIELD RESET R/W ADDR
7
6
5
4
PWMH
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
F04H, F0CH
Table 43. Timer 0-1 PWM Low Byte Register (TxPWML)
BITS FIELD RESET R/W ADDR
7
6
5
4
PWML
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
F05H, F0DH
PWMH and PWML--Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. When a match occurs, the PWM output changes state. The PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL) register. The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operating in CAPTURE or CAPTURE/COMPARE modes.
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Timer 0-3 Control 0 Registers
The Timer 0-3 Control 0 (TxCTL0) registers (Tables 44 and 45) allow cascading of the Timers.
Table 44. Timer 0-3 Control 0 Register (TxCTL0)
BITS FIELD RESET R/W ADDR
7
6
Reserved
5
4
CSC
3
2
Reserved
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
F06H, F0EH, F16H, F1EH
CSC--Cascade Timers 0 = Timer Input signal comes from the pin. 1 = For Timer 0, input signal is connected to Timer 1 output. For Timer 1, input signal is connected to Timer 0 output.
Timer 0-1 Control 1 Registers
The Timer 0-1 Control (TxCTL) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode.
Table 45. Timer 0-1 Control Register (TxCTL)
BITS FIELD RESET R/W ADDR
7
TEN 0 R/W
6
TPOL 0 R/W
5
4
PRES
3
2
1
TMODE
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
F07H, F0FH
TEN--Timer Enable 0 = Timer is disabled. 1 = Timer enabled to count. TPOL--Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT mode When the timer is disabled, the Timer Output signal is set to the value of this bit.
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When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. PWM mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. GATED mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal. PRES--Prescale value. The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This insures proper clock division
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each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE--Timer mode 000 = ONE-SHOT mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARE mode
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Watch-Dog Timer
Overview
The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8F082x family device into unsuitable operating states. The Watch-Dog Timer includes the following features:
* * * Operation
On-chip RC oscillator A selectable time-out response: Reset or interrupt 24-bit programmable time-out value
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the Z8F082x family device when the WDT reaches its terminal count. The Watch-Dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer has only two modes of operation--on and off. Once enabled, it always counts and must be refreshed to prevent a time-out. An enable can be performed by executing the WDT instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watch-Dog Timer to operate all the time, even if a WDT instruction has not been executed. The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is given by the following equation:
WDT Time-out Period (ms) = WDT Reload Value ------------------------------------------------10
where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator frequency is 10kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 45 provides
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information on approximate time-out delays for the minimum and maximum WDT reload values.
Table 45. Watch-Dog Timer Approximate Time-Out Delays Approximate Time-Out Delay (with 10kHz typical WDT oscillator frequency) Typical 400s 1677.5s Description Minimum time-out delay Maximum time-out delay
WDT Reload Value (Hex) 000004 FFFFFF
WDT Reload Value (Decimal) 4 16,777,215
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog Timer Reload registers. The Watch-Dog Timer then counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload registers. Counting resumes following the reload operation. When the Z8F082x family device is operating in DEBUG Mode (using the On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent spurious WatchDog Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the Watch-Dog Timer generates either an interrupt or a Reset. The WDT_RES Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chapter for information regarding programming of the WDT_RES Option Bit. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Watch-Dog Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watch-Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog Timer counter is not automatically returned to its Reload Value. WDT Reset in Stop Mode If enabled in STOP mode and configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to the Reset and STOP Mode Recovery
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chapter for more information. Default operation is for the WDT and its RC oscillator to be enabled during STOP mode. To minimize power consumption in Stop Mode, the WDT and its RC oscillator can be disabled in STOP mode. The following sequence configures the WDT to be disabled when the Z8F082x family device enters Stop Mode following execution of a Stop instruction: 1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write 81H to the Watch-Dog Timer Control register (WDTCTL) to configure the WDT and its oscillator to be disabled during Stop Mode. Alternatively, write 00H to the Watch-Dog Timer Control register (WDTCTL) as the third step in this sequence to reconfigure the WDT and its oscillator to be enabled during Stop Mode. This sequence only affects WDT operation in STOP mode. WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the device into the Reset state. The WDT status bit in the Watch-Dog Timer Control register is set to 1. Refer to the Reset and STOP Mode Recovery chapter for more information on Reset. WDT Reset in STOP Mode If enabled in STOP mode and configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to the Reset and STOP Mode Recovery chapter for more information. Default operation is for the WDT and its RC oscillator to be enabled during STOP mode. To minimize power consumption in Stop Mode, the WDT and its RC oscillator can be disabled in STOP mode. The following sequence configures the WDT to be disabled when the Z8F082x family device enters Stop Mode following execution of a Stop instruction: 1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write 81H to the Watch-Dog Timer Control register (WDTCTL) to configure the WDT and its oscillator to be disabled during Stop Mode. Alternatively, write 00H to the Watch-Dog Timer Control register (WDTCTL) as the third step in this sequence to reconfigure the WDT and its oscillator to be enabled during Stop Mode. This sequence only affects WDT operation in STOP mode.
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Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. The follow sequence is required to unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access. 1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU). 4. Write the Watch-Dog Timer Reload High Byte register (WDTH). 5. Write the Watch-Dog Timer Reload Low Byte register (WDTL). All three Watch-Dog Timer Reload registers must be written in the order just listed. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur, unless the sequence is restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.
Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register, detailed in Table 46, is a Read-Only register that indicates the source of the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0. Writing the 55H, AAH unlock sequence to the Watch-Dog Timer Control (WDTCTL) register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the
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WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers.
Table 46. Watch-Dog Timer Control Register (WDTCTL)
BITS FIELD RESET R/W ADDR
7
POR
6
STOP
5
WDT
4
EXT 0
3
2
Reserved
1
0
See descriptions below R R R
0 R FF0H
0 R
0 R
0 R
R
Reset or STOP Mode Recovery Event Power-On Reset Reset via RESET pin assertion Reset via Watch-Dog Timer time-out Reset via the On-Chip Debugger (OCTCTL[1] set to 1) Reset from STOP Mode through the DBG Pin driven Low STOP Mode Recovery via GPIO pin transition STOP Mode Recovery via Watch-Dog Timer time-out 1 0 0 1 1 0 0
POR
STOP 0 0 0 0 0 1 1 0 0 1 0 0 0 1
WDT 0 1 0 0 0 0 0
EXT
POR--Power-On Reset Indicator If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT timeout or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. STOP--STOP Mode Recovery Indicator If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode. Reading this register also resets this bit. WDT--Watch-Dog Timer Time-Out Indicator If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. EXT--External Reset Indicator If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit.
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Reserved These bits are reserved and must be 0.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) registers (Tables 47 through 49) form the 24-bit reload value that is loaded into the WatchDog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the desired Reload Value. Reading from these registers returns the current Watch-Dog Timer count value. Caution: The 24-bit WDT Reload Value must not be set to a value less than
000004H. Table 47. Watch-Dog Timer Reload Upper Byte Register (WDTU)
BITS FIELD RESET R/W ADDR
7
6
5
4
WDTU
3
2
1
0
1 R/W*
1 R/W*
1 R/W*
1 R/W* FF1H
1 R/W*
1 R/W*
1 R/W*
1 R/W*
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTU--WDT Reload Upper Byte Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 48. Watch-Dog Timer Reload High Byte Register (WDTH)
BITS FIELD RESET R/W ADDR
7
6
5
4
WDTH
3
2
1
0
1 R/W*
1 R/W*
1 R/W*
1 R/W* FF2H
1 R/W*
1 R/W*
1 R/W*
1 R/W*
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
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WDTH--WDT Reload High Byte Middle byte, Bits[15:8], of the 24-bit WDT reload value.
Table 49. Watch-Dog Timer Reload Low Byte Register (WDTL)
BITS FIELD RESET R/W ADDR
7
6
5
4
WDTL
3
2
1
0
1 R/W*
1 R/W*
1 R/W*
1 R/W* FF3H
1 R/W*
1 R/W*
1 R/W*
1 R/W*
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTL--WDT Reload Low Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
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UART
Overview
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include:
* * * * * * * * * * Architecture
8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking Option of one or two Stop bits Separate transmit and receive interrupts Framing, parity, overrun and break detection Separate transmit and receive enables 16-bit Baud Rate Generator (BRG) Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes Baud Rate Generator timer mode Driver Enable output for external bus transceivers
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART's transmitter and receiver function independently, but employ the same baud rate and data format. Figure 11 illustrates the UART architecture.
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Parity Checker Receiver Control with address compare RXD Receive Shifter
Receive Data Register
Control Registers
System Bus
Transmit Data Register
Status Register
Baud Rate Generator
TXD
Transmit Shift Register Transmitter Control Parity Generator
CTS DE
Figure 11. UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or odd parity bit can be optionally added to the data stream. Each character begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits.
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Figures 12 and 13 illustrates the asynchronous data format employed by the UART without parity and with parity, respectively.
Data Field Idle State of Line 1 Start 0 1 2 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 lsb msb Stop Bit(s)
Figure 12. UART Asynchronous Data Format without Parity
Data Field Idle State of Line 1 Start 0 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity lsb msb
Stop Bit(s)
1 2
Figure 13. UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled method of operation: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. If multiprocessor mode is desired, write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions. - Set the Multiprocessor Mode Select (MPEN) to Enable Multiprocessor mode. 4. Write to the UART Control 0 register to: - Set the transmit enable bit (TEN) to enable the UART for data transmission - If parity is desired and multiprocessor mode is not enabled, set the parity enable bit (PEN) and select either even or odd parity (PSEL).
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-
Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin.
5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data. 6. Write the UART Control 1 register to select the outgoing address bit. - Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 7. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 8. If desired and multiprocessor mode is enabled, make any changes to the Multiprocessor Bit Transmitter (MPBT) value. 9. To transmit additional bytes, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The UART Transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow these steps to configure the UART for interruptdriven data transmission: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the desired priority. 5. If multiprocessor mode is desired, write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions. - Set the Multiprocessor Mode Select (MPEN) to Enable Multiprocessor mode. 6. Write to the UART Control 0 register to: - Set the transmit enable bit (TEN) to enable the UART for data transmission - Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity. - Set or clear the CTSE bit to enable or disable control from the remote receiver via the CTS pin. 7. Execute an EI instruction to enable interrupts.
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The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write the UART Control 1 register to select the outgoing address bit: - Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 2. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty.
Receiving Data using the Polled Method
Follow these steps to configure the UART for polled data reception: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Write to the UART Control 1 register to enable Multiprocessor mode functions, if desired. 4. Write to the UART Control 0 register to: - Set the receive enable bit (REN) to enable the UART for data reception - Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity. 5. Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 5. If the Receive Data register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. 6. Read data from the UART Receive Data register. If operating in Multiprocessor (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. 7. Return to Step 4 to receive additional data.
Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow these steps to configure the UART receiver for interrupt-driven operation:
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1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority. 5. Clear the UART Receiver interrupt in the applicable Interrupt Request register. 6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode functions, if desired. - Set the Multiprocessor Mode Select (MPEN) to Enable Multiprocessor mode. - Set the Multiprocessor Mode Bits, MPMD[1:0], to select the desired address matching scheme. - Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a DMA block) 7. Write the device address to the Address Compare Register (automatic multiprocessor modes only). 8. Write to the UART Control 0 register to: - Set the receive enable bit (REN) to enable the UART for data reception - Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity. 9. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Check the UART Status 0 register to determine the source of the interrupt - error, break, or received data. 2. If the interrupt was due to data available, read the data from the UART Receive Data register. If operating in Multiprocessor (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. 3. Clear the UART Receiver interrupt in the applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and await more data.
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Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sampled one system clock before beginning any new character transmission. To delay transmission of the next data character, an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins. For multiple character transmissions, this would typically be done during Stop Bit transmission. If CTS deasserts in the middle of a character transmission, the current character is sent completely.
Multiprocessor (9-bit) Mode
The UART has a Multiprocessor (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common UART bus. In Multiprocessor mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immediately following the 8-bits of data and immediately preceding the Stop bit(s) as illustrated in Figure 14. The character format is:
Data Field Idle State of Line 1 Start 0 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 MP lsb msb
Stop Bit(s)
1 2
Figure 14. UART Asynchronous Multiprocessor Mode Data Format
In Multiprocessor (9-bit) mode, the Parity bit location (9th bit) becomes the Multiprocessor control bit. The UART Control 1 and Status 1 registers provide Multiprocessor (9-bit) mode control and status information. If an automatic address matching scheme is enabled, the UART Address Compare register holds the network address of the device. Multiprocessor (9-bit) Mode Receive Interrupts When multiprocessor mode is enabled, the UART will only process frames addressed to it. The determination of whether a frame of data is addressed to the UART can be made in hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, since it does not need to access the UART when it receives data directed to other devices on the multi-node network. The following three multi-processor modes are available in hardware:
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Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all multiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software should clear MPMD[0]. At this point, each new incoming byte will interrupt the CPU. The software is then responsible for determining the end of the frame. It will check for this by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, then a new frame has begun. If the address of this new frame is different from the UART's address, then MPMD[0] should be set to 1 causing the UART interrupts to go inactive until the next address byte. If the new frame's address matches the UART's, then the data in the new frame should be processed as well. Setting MPMD[1:0] to 10b and writing the UART's address into the UART Address Compare Register. This mode introduces more hardware control, interrupting only on frames that match the UART's address. When an incoming address byte does not match the UART's address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an interrupt is issued and further interrupts will now occur on each succesive data byte. The first data byte in the frame will have the NEWFRM=1 in the UART Status 1 Register. When the next address byte occurs, the hardware will compare it to the UART's address. If there is a match, the interrupts will continue and the NEWFRM bit will be set for the first byte of the new frame. If there is no match, then the UART to ignore all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART's address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame is still accompanied by a NEWFRM assertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi-transceiver bus, such as RS-485. Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 15. The Driver Enable signal asserts when a byte is written to the UART Transmit Data register. The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver Enable signal deasserts one system clock period after the last Stop bit is transmitted. This one system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determine if another character follows the current character. In
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the event of back to back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted) the DE signal is not deasserted between characters. The DEPOL bit in the UART Control Register 1 sets the polarity of the Driver Enable signal.
1 DE 0 Data Field Idle State of Line 1 Start 0 1 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity lsb msb Stop Bit
Figure 15. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
1 2 ------------------------------------ DE to Start Bit Setup Time (s) ------------------------------------ Baud Rate (Hz) Baud Rate (Hz) UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out. At this point, the Transmit Data register may be written with the next character to send. This provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the TDRE bit to 0. Receiver Interrupts The receiver generates an interrupt when any of the following occurs:
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A data byte has been received and is available in the UART Receive Data register. This interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in the Receive Data register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. Note that in multiprocessor mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte. A break is received An overrun is detected A data framing error is detected
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UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and should be ignored. The BRKD bit indicates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received.
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UART Data and Error Handling Procedure Figure 16 illustrates the recommended procedure for use in UART receiver interrupt service routines.
Receiver Ready
Receiver Interrupt
Read Status
No Errors?
Yes Read Data which clears RDA bit and resets error bits
Read Data
Discard Data
Figure 16. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This action allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
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High and Low Byte registers combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data rate is calculated using the following equation:
System Clock Frequency (Hz) UART Data Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register to 0. 2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the UART Control 1 register to 1.
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/ Decoders. For more information on the infrared operation, refer to the Infrared Encoder/ Decoder chapter on page 102.
UART Transmit Data Register
Data bytes written to the UART Transmit Data register (Table 50) are shifted out on the TXDx pin. The Write-only UART Transmit Data register shares a Register File address with the Read-only UART Receive Data register.
Table 50. UART Transmit Data Register (U0TXD)
BITS FIELD RESET R/W ADDR
7
6
5
4
TXD
3
2
1
0
X W
X W
X W
X W F40H
X W
X W
X W
X W
TXD--Transmit Data UART transmitter data byte to be shifted out through the TXDx pin.
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UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data register (Table 51). The Read-only UART Receive Data register shares a Register File address with the Write-only UART Transmit Data register.
Table 51. UART Receive Data Register (U0RXD)
BITS FIELD RESET R/W ADDR
7
6
5
4
RXD
3
2
1
0
X R
X R
X R
X R F40H
X R
X R
X R
X R
RXD--Receive Data UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 52 and 53) identify the current UART operating configuration and status.
Table 52. UART Status 0 Register (U0STAT0)
BITS FIELD RESET R/W ADDR
7
RDA 0 R
6
PE 0 R
5
OE 0 R
4
FE 0 R F41H
3
BRKD 0 R
2
TDRE 1 R
1
TXE 1 R
0
CTS X R
RDA--Receive Data Available This bit indicates that the UART Receive Data register has received data. Reading the UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register. PE--Parity Error This bit indicates that a parity error has occurred. Reading the UART Receive Data register clears this bit.
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0 = No parity error has occurred. 1 = A parity error has occurred. OE--Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has not been read. If the RDA bit is reset to 0, then reading the UART Receive Data register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. FE--Framing Error This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. BRKD--Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears this bit. 0 = No break occurred. 1 = A break occurred. TDRE--Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data. Writing to the UART Transmit Data register resets this bit. 0 = Do not write to the UART Transmit Data register. 1 = The UART Transmit Data register is ready to receive an additional byte to be transmitted. TXE--Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is finished. 0 = Data is currently transmitting. 1 = Transmission is complete.
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CTS--CTS signal When this bit is read it returns the level of the CTS signal.
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 53. UART Status 1 Register (U0STAT1)
BITS FIELD RESET R/W ADDR
7
6
5
Reserved
4
3
2
1
NEWFRM
0
MPRX 0 R
0 R
0 R
0 R
0 R F44H
0 R/W
0 R/W
0 R
Reserved--Must be 0. NEWFRM--Status bit denoting the start of a new frame. Reading the UART Receive Data register resets this bit to 0. 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. MPRX--Multiprocessor Receive Returns the value of the last multiprocessor bit received. Reading from the UART Receive Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (Tables 54 and 55) configure the properties of the UART's transmit and receive operations. The UART Control registers must not been written while the UART is enabled.
Table 54. UART Control 0 Register (U0CTL0)
BITS FIELD RESET R/W ADDR
7
TEN 0 R/W
6
REN 0 R/W
5
CTSE 0 R/W
4
PEN 0 R/W F42H
3
PSEL 0 R/W
2
SBRK 0 R/W
1
STOP 0 R/W
0
LBEN 0 R/W
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TEN--Transmit Enable This bit enables or disables the transmitter. The enable is also controlled by the CTS signal and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled. 0 = Transmitter disabled. 1 = Transmitter enabled. REN--Receive Enable This bit enables or disables the receiver. 0 = Receiver disabled. 1 = Receiver enabled. CTSE--CTS Enable 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. PEN--Parity Enable This bit enables or disables parity. Even or odd is determined by the PSEL bit. 0 = Parity is disabled. 1 = The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit. PSEL--Parity Select 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. SBRK--Send Break This bit pauses or breaks data transmission. Sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending data before setting this bit. 0 = No break is sent. 1 = The output of the transmitter is zero. STOP--Stop Bit Select 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits.
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LBEN--Loop Back Enable 0 = Normal operation. 1 = All transmitted data is looped back to the receiver.
Table 55. UART Control 1 Register (U0CTL1)
BITS FIELD RESET R/W ADDR
7
MPMD[1] 0 R/W
6
MPEN 0 R/W
5
MPMD[0] 0 R/W
4
MPBT 0 R/W F43H
3
DEPOL 0 R/W
2
BRGCTL 0 R/W
1
RDAIRQ 0 R/W
0
IREN 0 R/W
MPMD[1:0]--Multiprocessor Mode If Multiprocessor (9-bit) mode is enabled, 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. 10 = The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Registr and on all successive data bytes until an address mismatch occurs. 11 = The UART generates an interrupt reques on all received data bytes for which the most recent address byte matched the value in the Address Compare Register. MPEN--Multiprocessor (9-bit) Enable This bit is used to enable Multiprocessor (9-bit) mode. 0 = Disable Multiprocessor (9-bit) mode. 1 = Enable Multiprocessor (9-bit) mode. MPBT--Multiprocessor Bit Transmit This bit is applicable only when Multiprocessor (9-bit) mode is enabled. 0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit). 1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit). DEPOL--Driver Enable Polarity 0 = DE signal is Active High. 1 = DE signal is Active Low. BRGCTL--Baud Rate Control This bit causes different UART behavior depending on whether the UART receiver is enabled (REN = 1 in the UART Control 0 Register). When the UART receiver is not enabled, this bit determines whether the Baud Rate Generator will issue interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 = The Baud Rate Generator generates a receive interrupt when it counts down to zero.
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Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low Byte is read. RDAIRQ--Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Controller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request. IREN--Infrared Encoder/Decoder Enable 0 = Infrared Encoder/Decoder is disabled. UART operates normally operation. 1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through the Infrared Encoder/Decoder.
UART Address Compare Register
The UART Address Compare register stores the multi-node network address of the UART. When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes will be compared to the value stored in the Address Compare register. Receive interrupts and RDA assertions will only occur in the event of a match.
Table 56. UART Address Compare Register (U0ADDR)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
COMP_ADDR 0 R/W 0 R/W 0 R/W 0 R/W F45H 0 R/W 0 R/W 0 R/W 0 R/W
COMP_ADDR--Compare Address This 8-bit value is compared to the any incoming address bytes.
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UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (Tables 57 and 57) combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART.
Table 57. UART Baud Rate High Byte Register (U0BRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRH
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W F46H
1 R/W
1 R/W
1 R/W
1 R/W
Table 58. UART Baud Rate Low Byte Register (U0BRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRL
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W F47H
1 R/W
1 R/W
1 R/W
1 R/w
The UART data rate is calculated using the following equation:
System Clock Frequency (Hz) UART Baud Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
For a given UART data rate, the integer baud rate divisor value is calculated using the following equation:
System Clock Frequency (Hz) UART Baud Rate Divisor Value (BRG) = Round --------------------------------------------------------------------------- 16 x UART Data Rate (bits/s)
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The baud rate error relative to the desired baud rate is calculated using the following equation:
Actual Data Rate - Desired Data Rate UART Baud Rate Error (%) = 100 x ------------------------------------------------------------------------------------------------ Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent. Table 59 provides information on data rate errors for popular baud rates and commonly used crystal oscillator frequencies.
Table 59. UART Baud Rates 10.0 MHz System Clock Desired Rate BRG Divisor Actual Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 (Decimal) N/A 1 3 5 11 16 33 65 130 260 521 1042 2083 (kHz) N/A 625.0 208.33 125.0 56.8 39.1 18.9 9.62 4.81 2.40 1.20 0.60 0.30 Error (%) N/A 0.00 -16.67 8.51 -1.36 1.73 0.16 0.16 0.16 -0.03 -0.03 -0.03 0.2 5.5296 MHz System Clock Desired Rate BRG Divisor Actual Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 (Decimal) N/A N/A 1 3 6 9 18 36 72 144 288 576 1152 (kHz) N/A N/A 345.6 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 Error (%) N/A N/A 38.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
3.579545 MHz System Clock Desired Rate BRG Divisor Actual Rate (kHz) 1250.0 625.0 250.0 (Decimal) N/A N/A 1 (kHz) N/A N/A 223.72 Error (%) N/A N/A -10.51
1.8432 MHz System Clock Desired Rate BRG Divisor Actual Rate (kHz) 1250.0 625.0 250.0 (Decimal) N/A N/A N/A (kHz) N/A N/A N/A Error (%) N/A N/A N/A
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Table 59. UART Baud Rates (Continued) 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 2 4 6 12 23 47 93 186 373 746 111.9 55.9 37.3 18.6 9.73 4.76 2.41 1.20 0.60 0.30 -2.90 -2.90 -2.90 -2.90 1.32 -0.83 0.23 0.23 -0.04 -0.04 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 1 2 3 6 12 24 48 96 192 384 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
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Infrared Encoder/Decoder
Overview
The Z8F082x family products contain a fully-functional, high-performance UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an on-chip UART to allow easy communication between the Z8 Encore!(R) and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communication provides secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell phones, printers and other infrared enabled devices.
Architecture
Figure 17 illustrates the architecture of the Infrared Endec.
System Clock RxD TxD UART Baud Rate Clock Infrared Encoder/Decoder (Endec) RXD
ZiLOG ZHX1810 RXD TXD TXD Infrared Transceiver
Interrupt I/O Signal Address
Data
Figure 17. Infrared Data Communication System Block Diagram
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Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver via the TXD pin. Likewise, data received from the infrared transceiver is passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART's Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec data rate is calculated using the following equation:
System Clock Frequency (Hz) Infrared Data Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The UART's transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16-clock data period. Figure 18 illustrates IrDA data transmission. When the Infrared Endec is enabled, the UART's TXD signal is internal to the Z8F082x family products while the IR_TXD signal is output through the TXD pin.
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16-clock period
Baud Rate Clock
UART's TXD
Start Bit = 0 3-clock pulse
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_TXD 7-clock delay
Figure 18. Infrared Data Transmission
Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART's baud rate clock is used by the Infrared Endec to generate the demodulated signal (RXD) that drives the UART. Each UART/Infrared data bit is 16-clocks wide. Figure 19 illustrates data reception. When the Infrared Endec is enabled, the UART's RXD signal is internal to the Z8F082x family products while the IR_RXD signal is received through the RXD pin.
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16-clock period
Baud Rate Clock Start Bit = 0 IR_RXD min. 1.6s pulse UART's RXD 8-clock delay Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
16-clock period
16-clock period
16-clock period
16-clock period
Figure 19. Infrared Data Reception
Caution:
The system clock frequency must be at least 1.0MHz to ensure proper reception of the 1.6s minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate an input stream for the UART and to create a sampling window for detection of incoming pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream. When a falling edge in the input data stream is detected, the Endec counter is reset. When the count reaches a value of 8, the UART RXD value is updated to reflect the value of the decoded data. When the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. The window remains open until the count again reaches 8 (or in other words 24 baud clock periods since the previous pulse was detected). This gives the Endec a sampling window of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock counter is reset, resynchronizing the Endec to the incoming signal. This allows the Endec to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchronized to the incoming data stream when a Start bit is received.
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Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control registers as defined beginning on page 92. Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO Port alternate function for the corresponding pin.
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Serial Peripheral Interface
Overview
The Serial Peripheral InterfaceTM (SPI) is a synchronous interface allowing several SPItype devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-toDigital Converters, and ISDN devices. Features of the SPI include:
* * * * *
Full-duplex, synchronous, character-oriented communication Four-wire interface Data transfers rates up to a maximum of one-half the system clock frequency Error detection Dedicated Baud Rate Generator
The SPI is unavailable in 20-pin package devices.
Architecture
The SPI may be configured as either a Master (in single or multi-master systems) or a Slave as illustrated in Figures 20 through 22.
SPI Master
To Slave's SS Pin From Slave
SS MISO 8-bit Shift Register Bit 7 MOSI Bit 0
To Slave
To Slave
SCK
Baud Rate Generator
Figure 20. SPI Configured as a Master in a Single Master, Single Slave System
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VCC
SPI Master SS To Slave #2's SS Pin To Slave #1's SS Pin From Slave MISO To Slave MOSI GPIO GPIO 8-bit Shift Register Bit 7 Bit 0
To Slave
SCK
Baud Rate Generator
Figure 21. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave From Master SS
To Master
MISO
8-bit Shift Register Bit 7 Bit 0
From Master
MOSI
From Master
SCK
Figure 22. SPI Configured as a Slave
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (serial clock, transmit, receive and Slave select). The SPI block consists of a transmit/receive shift register, a Baud Rate (clock) Generator and a control unit.
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During an SPI transfer, data is sent and received simultaneously by both the Master and the Slave SPI devices. Separate signals are required for data and the serial clock. When an SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register in the Master and another 8-bit shift register in the Slave are connected as a circular buffer. The SPI shift register is single-buffered in the transmit and receive directions. New data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
* * * *
MISO (Master-In, Slave-Out) MOSI (Master-Out, Slave-In) SCK (Serial Clock) SS (Slave Select)
The following paragraphs discuss these SPI signals. Each signal is described in both Master and Slave modes. Master-In, Slave-Out The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as an output in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance state if the Slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state. Master-Out, Slave-In The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as an input in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance state. Serial Clock The Serial Clock (SCK) synchronizes data movement both in and out of the device through its MOSI and MISO pins. In MASTER mode, the SPI's Baud Rate Generator creates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave's SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock signal from the Master synchronizes the data transfer between the Master and Slave devices. Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times the system (XIN) clock period.
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The Master and Slave are each capable of exchanging a character of data during a sequence of NUMBITS clock cycles (refer to NUMBITS field in the SPIMODE register). In both Master and Slave SPI devices, data is shifted on one edge of the SCK and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI phase and polarity control. Slave Select The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low prior to all data communication to and from the Slave device. SS must stay Low for the full duration of each character transferred. The SS signal may stay Low during the transfer of multiple characters or may deassert between each character. When the SPI is configured as the only Master in an SPI system, the SS pin can be set as either an input or an output. For communication between the Z8F082x family device's SPI Master and external Slave devices, the SS signal, as an output, can assert the SS input pin on one of the Slave devices. Other GPIO output pins can also be employed to select external SPI Slave devices. When the SPI is configured as one Master in a multi-master SPI system, the SS pin should be set as an input. The SS input signal on the Master must be High. If the SS signal goes Low (indicating another Master is driving the SPI bus), a Collision error flag is set in the SPI Status register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the SPI Control register. The clock polarity bit, CLKPOL, selects an active high or active low clock and has no effect on the transfer format. Table 60 lists the SPI Clock Phase and Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamentally different transfer formats. For proper data transmission, the clock phase and polarity must be identical for the SPI Master and the SPI Slave. The Master always places data on the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the Slave to latch the data.
Table 60. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation SCK Transmit Edge Falling Rising Rising Falling SCK Receive Edge Rising Falling Falling Rising SCK Idle State Low High Low High
PHASE
0 0 1 1
CLKPOL
0 1 0 1
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Transfer Format PHASE Equals Zero Figure 23 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to one. The diagram may be interpreted as either a Master or Slave timing diagram since the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly connected between the Master and the Slave.
SCK (CLKPOL = 0)
SCK (CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 23. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One Figure 24 illustrates the timing diagram for an SPI transfer in which PHASE is one. Two waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL set to 1.
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SCK (CLKPOL = 0)
SCK (CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 24. SPI Timing When PHASE is 1
Multi-Master Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied together and all MISO pins are tied together. All SPI pins must then be configured in OPEN-DRAIN mode to prevent bus contention. At any one time, only one SPI device is configured as the Master and all other SPI devices on the bus are configured as Slaves. The Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves (including those which are not enabled). The enabled Slave drives data out its MISO pin to the MISO Master pin. For a Master device operating in a multi-master system, if the SS pin is configured as an input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Register. The COL bit indicates the occurrence of a multi-master collision (mode fault error condition).
Slave Operation
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and the MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE
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register. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS field in the SPIMODE register must be set to be consistent with the other SPI devices. The STR bit in the SPICTL register may be used if desired to force a "startup" interrupt. The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE mode so the SPIBRH and SPIBRL registers need not be initialized. If the slave has data to send to the master, the data should be written to the SPIDAT register before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT register is not written prior to the slave transaction, the MISO pin outputs whatever value is currently in the SPIDAT register. Due to the delay resulting from synchronization of the SPI input signals to the internal system clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is the system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recognize when communication errors have occurred. The SPI Status register indicates when a data transmission error has been detected. Overrun (Write Collision) An overrun error (write collision) indicates a write to the SPI Data register was attempted while a data transfer is in progress (in either master or slave modes). An overrun sets the OVR bit in the SPI Status register to 1. Writing a 1 to OVR clears this error flag. The data register is not altered when a write occurs while data transfer is in progress. Mode Fault (Multi-Master Collision) A mode fault indicates when more than one Master is trying to communicate at the same time (a multi-master collision). The mode fault is detected when the enabled Master's SS pin is asserted. A mode fault sets the COL bit in the SPI Status register to 1. Writing a 1 to COL clears this error flag. SLAVE Mode Abort In SLAVE mode, if the SS pin deasserts before all bits in a character have been transferred, the transaction aborts. When this condition occurs the ABT bit is set in the SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous transaction left off. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception completes in both master and slave modes. A character can be defined to be
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1 through 8 bits by the NUMBITS field in the SPI Mode register. In SLAVE mode it is not necessary for SS to deassert between characters to generate the interrupt. The SPI in SLAVE mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits in a character (see description of slave abort error above). Writing a 1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts. To start the transfer process, an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL register. If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator timeout. This timer function must be enabled by setting the BIRQ bit in the SPICTL register. This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI MASTER mode, the Baud Rate Generator creates a lower frequency serial clock (SCK) for data transmission synchronization between the Master and the external Slave. The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz) SPI Baud Rate (bits/s) = --------------------------------------------------------------------------2 x BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value of (2 X 65536 = 131072). When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0. 2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the SPI Control register to 1.
SPI Control Register Definitions
SPI Data Register
The SPI Data register stores both the outgoing (transmit) data and the incoming (receive) data. Reads from the SPI Data register always return the current contents of the 8-bit shift
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register. Data is shifted out starting with bit 7. The last bit received resides in bit position 0. With the SPI configured as a Master, writing a data byte to this register initiates the data transmission. With the SPI configured as a Slave, writing a data byte to this register loads the shift register in preparation for the next data transfer with the external Master. In either the Master or Slave modes, if a transmission is already in progress, writes to this register are ignored and the Overrun error flag, OVR, is set in the SPI Status register. When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode register), the transmit character must be left justified in the SPI Data register. A received character of less than 8 bits is right justified (last bit received is in bit position 0). For example, if the SPI is configured for 4-bit characters, the transmit characters must be written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
Table 61. SPI Data Register (SPIDATA)
BITS FIELD RESET R/W ADDR
7
6
5
4
DATA
3
2
1
0
X R/W
X R/W
X R/W
X R/W F60H
X R/W
X R/W
X R/W
X R/W
DATA--Data Transmit and/or receive data.
SPI Control Register
The SPI Control register configures the SPI for transmit and receive operations.
Table 62. SPI Control Register (SPICTL)
BITS FIELD RESET R/W ADDR
7
IRQE 0 R/W
6
STR 0 R/W
5
BIRQ 0 R/W
4
PHASE 0 R/W F61H
3
CLKPOL 0 R/W
2
WOR 0 R/W
1
MMEN 0 R/W
0
SPIEN 0 R/W
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IRQE--Interrupt Request Enable 0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller. 1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller. STR--Start an SPI Interrupt Request 0 = No effect. 1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by software for a function similar to transmit buffer empty in a UART. Writing a 1 to the IRQ bit in the SPI Status register clears this bit to 0. BIRQ--BRG Timer Interrupt Request If the SPI is enabled, this bit has no effect. If the SPI is disabled: 0 = The Baud Rate Generator timer function is disabled. 1 = The Baud Rate Generator timer function and time-out interrupt are enabled. PHASE--Phase Select Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and Polarity Control section for more information on operation of the PHASE bit. CLKPOL--Clock Polarity 0 = SCK idles Low (0). 1 = SCK idle High (1). WOR--Wire-OR (Open-Drain) Mode Enabled 0 = SPI signal pins not configured for open-drain. 1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function. This setting is typically used for multi-master and/or multi-slave configurations. MMEN--SPI MASTER Mode Enable 0 = SPI configured in SLAVE mode. 1 = SPI configured in MASTER mode. SPIEN--SPI Enable 0 = SPI disabled. 1 = SPI enabled.
SPI Status Register
The SPI Status register indicates the current state of the SPI. All bits revert to their reset state if the SPIEN bit in the SPICTL register = 0.
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Table 63. SPI Status Register (SPISTAT)
BITS FIELD RESET R/W ADDR
7
IRQ 0 R/W*
6
OVR 0 R/W*
5
COL 0 R/W*
4
ABT 0 R/W* F62H
3
Reserved 0 R
2
1
TXST 0 R
0
SLAS 1 R
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ--Interrupt Request If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud Rate Generator is used as a timer to generate the SPI interrupt. 0 = No SPI interrupt request pending. 1 = SPI interrupt request is pending. OVR--Overrun 0 = An overrun error has not occurred. 1 = An overrun error has been detected. COL--Collision 0 = A multi-master collision (mode fault) has not occurred. 1 = A multi-master collision (mode fault) has been detected. ABT--SLAVE mode transaction abort This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS deasserts before all bits of a character have been transferred as defined by the NUMBITS field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has completed. 0 = A SLAVE mode transaction abort has not occurred. 1 = A SLAVE mode transaction abort has been detected. Reserved--Must be 0. TXST--Transmit Status 0 = No data transmission currently in progress. 1 = Data transmission currently in progress. SLAS--Slave Select If SPI enabled as a Slave, 0 = SS input pin is asserted (Low) 1 = SS input is not asserted (High). If SPI enabled as a Master, this bit is not applicable.
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SPI Mode Register
The SPI Mode register configures the character bit width and the direction and value of the SS pin.
Table 64. SPI Mode Register (SPIMODE)
BITS FIELD RESET R/W ADDR
7
Reserved 0 R
6
5
DIAG 0 R/W
4
3
NUMBITS[2:0]
2
1
SSIO
0
SSV 0 R/W
0 R/W F63H
0 R/W
0 R/W
0 R/W
Reserved--Must be 0. DIAG - Diagnostic Mode Control bit This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be read using the SPIBRH and SPIBRL register locations. 0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers 1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and Low byte values are not buffered. Caution: Exercise caution if reading the values while the BRG is counting.
NUMBITS[2:0]--Number of Data Bits Per Character to Transfer This field contains the number of bits to shift for each character transfer. Refer to the SPI Data Register description for information on valid bit positions when the character length is less than 8-bits. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits 110 = 6 bits 111 = 7 bits. SSIO--Slave Select I/O 0 = SS pin configured as an input. 1 = SS pin configured as an output (MASTER mode only).
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SSV--Slave Select Value If SSIO = 1 and SPI configured as a Master: 0 = SS pin driven Low (0). 1 = SS pin driven High (1). This bit has no effect if SSIO = 0 or SPI configured as a Slave.
SPI Diagnostic State Register
The SPI Diagnostic State register provides observability of internal state. This is a read only register used for SPI diagnostics.
Table 65. SPI Diagnostic State Register (SPIDST)
BITS FIELD RESET R/W ADDR
7
SCKEN 0 R
6
TCKEN 0 R
5
4
3
2
SPISTATE 0 R
1
0
F64H
SCKEN - Shift Clock Enable 0 = The internal Shift Clock Enable signal is deasserted 1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next system clock) TCKEN - Transmit Clock Enable 0 = The internal Transmit Clock Enable signal is deasserted. 1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial data out is updated on the next system clock (MOSI or MISO). SPISTATE - SPI State Machine Defines the current state of the internal SPI State Machine.
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SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz) SPI Baud Rate (bits/s) = --------------------------------------------------------------------------2 x BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value of (2 X 65536 = 131072).
Table 66. SPI Baud Rate High Byte Register (SPIBRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRH
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W F66H
1 R/W
1 R/W
1 R/W
1 R/W
BRH = SPI Baud Rate High Byte Most significant byte, BRG[15:8], of the SPI Baud Rate Generator's reload value.
Table 67. SPI Baud Rate Low Byte Register (SPIBRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRL
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W F67H
1 R/W
1 R/W
1 R/W
1 R/w
BRL = SPI Baud Rate Low Byte Least significant byte, BRG[7:0], of the SPI Baud Rate Generator's reload value.
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I2C Controller
Overview
The I2C Controller makes the Z8F082x family products bus-compatible with the I2CTM protocol. The I2C Controller consists of two bidirectional bus lines--a serial data signal (SDA) and a serial clock signal (SCL). Features of the I2C Controller include:
* * * *
Transmit and Receive Operation in MASTER mode Maximum data rate of 400kbit/sec 7- and 10-bit Addressing Modes for Slaves Unrestricted Number of Data Bytes Transmitted per Transfer
The I2C Controller in the Z8F082x family products does not operate in SLAVE mode.
Operation
The I2C Controller operates in MASTER mode to transmit and receive data. Only a single master is supported. Arbitration between two masters must be accomplished in software. I2C supports the following operations:
* * * *
Master transmits to a 7-bit slave Master transmits to a 10-bit slave Master receives from a 7-bit slave Master receives from a 10-bit slave
SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin alternate functions are selected for their respective GPIO ports, the pins are automatically configured for open-drain operation. The master (I2C) is responsible for driving the SCL clock signal, although the clock signal can become skewed by a slow slave device. During the Low period of the clock, the slave pulls the SCL signal Low to suspend the transaction. The master releases the clock at the end of the Low period and notices that the clock remains Low instead of returning to a
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High level. When the slave has released the clock, the I2C Controller continues the transaction. All data is transferred in bytes and there is no limit to the amount of data transferred in one operation. When transmitting data or acknowledging read data from the slave, the SDA signal changes in the middle of the Low period of SCL and is sampled in the middle of the high period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts--Transmit, Receive, Not Acknowledge (NAK) and baud rate generator. These four interrupt sources are combined into a single interrupt request signal to the interrupt controller. NAK interrupts occur when a Not Acknowledge is received from the slave or sent by the I2C Controller and the Start or Stop bit is not set. The NAK event sets bit 0 of the I2CSTAT register and can only be cleared by setting the Start or Stop bit. When this interrupt occurs, the I2C Controller waits until it is cleared before performing any action. In an interrupt service routine, the NAK interrupt must be the first item polled. Receive interrupts occur when a byte of data has been received by the I2C master. The receive interrupt is cleared by reading from the I2C Data register. If no action is taken, the I2C Controller waits until this interrupt is cleared before performing any other action. For Transmit interrupts to occur, the TXI bit must be 1 in the I2C Control register. Transmit interrupts occur under the following conditions when the transmit data register is empty:
* * * *
The I2C Controller is enabled The first bit of the byte of an address is shifting out and the RD bit of the I2C Status register is deasserted The first bit of a 10-bit address shifts out The first bit of write data shifted out
Note: Writing to the I2C Data register always clears the TRDE bit to 0. The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled (IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an interrupt is generated when the baud rate generator counts down to 1.
Start and Stop Conditions
The master (I2C) drives all Start and Stop signals and initiates all transactions. To start a transaction, the I2C Controller generates a START condition by pulling the SDA signal low while SCL is High. To complete a transaction, the I2C Controller generates a Stop condition by creating a Low-to-High transition of the SDA signal while the SCL signal is High. The Start and Stop signals are found in the I2C Control register and must be written by software when the Z8F082x family device must begin or end a transaction.
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Write Transaction with a 7-Bit Address
Figure 25 illustrates the data transfer format for a 7-bit addressed slave. Shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A P/S
Figure 25. 7-Bit Addressed Slave Data Transfer Format
The procedure for a transmit operation on a 7-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I2C interrupt asserts, because the I2C Data register is empty 4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0) to the I2C Data register. 5. Software asserts the START bit of the I2C Control register. 6. The I2C Controller sends the START condition to the I2C slave. 7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt is asserted. 9. Software responds by writing the transmit data into the I2C Data register. 10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal. 11. The I2C slave sends an acknowledge (by pulling the SDA signal Low) during the next high period of SCL. The I2C Controller sets the ACK bit in the I2C Status register. 12. The I2C Controller loads the contents of the I2C Shift register with the contents of the I2C Data register. 13. The I2C Controller shifts the data out of via the SDA signal. After the first bit is sent, the Transmit interrupt is asserted. 14. If more bytes remain to be sent, return to step 9 15. Software responds by setting the STOP bit of the I2C Control register (or START bit to initiate a new transaction). 16. If no new data is to be sent or address is to be sent, software responds by clearing the TXI bit of the I2C Control register.
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17. The I2C Controller completes transmission of the data on the SDA signal. 18. The I2C Controller sends the STOP condition to the I2C bus.
Write Transaction with a 10-Bit Address
Figure 26 illustrates the data transfer format for a 10-bit addressed slave. Shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S Slave Address 1st 7 bits W=0 A Slave Address 2nd Byte A Data A Data A/A P/S
Figure 26. 10-Bit Addressed Slave Data Transfer Format
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the read/write control bit (=0). The transmit operation is carried out in the same manner as 7bit addressing. The procedure for a transmit operation on a 10-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I2C interrupt asserts because the I2C Data register is empty. 4. Software responds to the TDRE interrupt by writing the first slave address byte. The least-significant bit must be 0 for the write operation. 5. Software asserts the START bit of the I2C Control register. 6. The I2C Controller sends the START condition to the I2C slave. 7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is asserted. 9. Software responds by writing the second byte of address into the contents of the I2C Data register. 10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA signal. 11. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL. The I2C Controller sets the ACK bit in the I2C Status register. 12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register.
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13. The I2C Controller shifts the second address byte out the SDA signal. After the first bit has been sent, the Transmit interrupt is asserted. 14. Software responds by writing the data to be written out to the I2C Control register. 15. The I2C Controller shifts out the rest of the second byte of slave address by the SDA signal. 16. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next High period of SCL. The I2C Controller sets the ACK bit in the I2C Status register. 17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the Transmit interrupt is asserted. 18. Software responds by asserting the STOP bit of the I2C Control register. 19. The I2C Controller completes transmission of the data on the SDA signal. 20. The I2C Controller sends the STOP condition to the I2C bus.
Read Transaction with a 7-Bit Address
Figure 27 illustrates the data transfer format for a read operation to a 7-bit addressed slave. The shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 27. Receive Data Transfer Format for a 7-Bit Addressed Slave
The procedure for a read operation to a 7-bit addressed slave is as follows: 1. Software writes the I2C Data register with a 7-bit slave address plus the read bit (=1). 2. Software asserts the START bit of the I2C Control register. 3. If this is a single byte transfer, Software asserts the NAK bit of the I2C Control register so that after the first byte of data has been read by the I2C Controller, a Not Acknowledge is sent to the I2C slave. 4. The I2C Controller sends the START condition. 5. The I2C Controller sends the address and read bit out the SDA signal. 6. The I2C slave acknowledges the address by pulling the SDA signal Low during the next High period of SCL. 7. The I2C Controller shifts in the first byte of data from the I2C slave on the SDA signal. 8. The I2C Controller asserts the Receive interrupt.
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9. Software responds by reading the I2C Data register. 10. The I2C Controller sends a NAK to the I2C slave (if this is the last byte). 11. If there are more bytes to transfer, return to step 7. 12. A NAK interrupt is generated by the I2C Controller. 13. Software responds by setting the STOP bit of the I2C Control register. 14. A STOP condition is sent to the I2C slave.
Read Transaction with a 10-Bit Address
Figure 28 illustrates the read transaction format for a 10-bit addressed slave. The shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S Slave Address 1st 7 bits W=0 A Slave Address A 2nd Byte
S
Slave Address R=1 1st 7 bits
A
Data
A
Data
A
P
Figure 28. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the write control bit. The data transfer procedure for a read operation to a 10-bit addressed slave is as follows: 1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C Data register. 2. Software asserts the START bit of the I2C Control register. 3. The I2C Controller sends the Start condition. 4. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 5. After the first bit has been shifted out, a Transmit interrupt is asserted. 6. Software responds by writing eight bits of address to the I2C Data register. 7. The I2C Controller completes shifting of the two address bits and a 0 (write). 8. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next High period of SCL. 9. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (lower byte of 10 bit address).
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10. The I2C Controller shifts out the next eight bits of address. After the first bit is shifted, the I2C Controller generates a Transmit interrupt. 11. Software responds by setting the START bit of the I2C Control register to generate a repeated START. 12. Software responds by writing 11110B followed by the 2-bit slave address and a 1 (read) to the I2C Data register. 13. If you want to read only one byte, software responds by setting the NAK bit of the I2C Control register. 14. After the I2C Controller shifts out the address bits mentioned in step 9 (2nd address transfer), the I2C slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL. 15. The I2C Controller sends the repeated START condition. 16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (third address transfer). 17. The I2C Controller sends 11110B followed by the two most significant bits of the slave read address and a 1 (read). 18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL. 19. The I2C Controller shifts in a byte of data from the slave. 20. A Receive interrupt is generated. 21. Software responds by reading the I2C Data register. 22. Software responds by setting the STOP bit of the I2C Control register. 23. A NAK condition is sent to the I2C slave. 24. A STOP condition is sent to the I2C slave.
I2C Control Register Definitions
I2C Data Register
The I2C Data register holds the data that is to be loaded into the I2C Shift register during a write to a slave. This register also holds data that is loaded from the I2C Shift register dur-
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ing a read from a slave. The I2C Shift Register is not accessible in the Register File address space, but only buffers incoming and outgoing data.
Table 68. I2C Data Register (I2CDATA)
BITS FIELD RESET R/W ADDR
7
6
5
4
DATA
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W F50H
0 R/W
0 R/W
0 R/W
0 R/W
I2C Status Register
The Read-only I2C Status register indicates the status of the I2C Controller.
Table 69. I2C Status Register (I2CSTAT)
BITS FIELD RESET R/W ADDR
7
TDRE 1 R
6
RDRF 0 R
5
ACK 0 R
4
10B 0 R F51H
3
RD 0 R
2
TAS 0 R
1
DSS 0 R
0
NCKI 0 R
TDRE--Transmit Data Register Empty When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty. When active, this bit causes the I2C Controller to generate an interrupt, except when the I2C Controller is shifting in data during the reception of a byte or when shifting an address and the RD bit is set. Writing to the I2CDATA register clears this bit and the interrupt. RDRF--Receive Data Register Full This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt. Reading the I2C Data register clears this bit. ACK--Acknowledge This bit indicates the status of the Acknowledge for the last byte transmitted or received. When set, this bit indicates that an Acknowledge was received for the last byte transmitted or received.
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10B--10-Bit Address This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit is set, if the five most-significant bits of the address are 11110B, this bit is set. When set, it is reset once the first byte of the address has been sent. RD--Read This bit indicates the direction of transfer of the data. It is active high during a read. The status of this bit is determined by the least-significant bit of the I2C Shift register after the START bit is set. TAS--Transmit Address State This bit is active high while the address is being shifted out of the I2C Shift register. DSS--Data Shift State This bit is active high while data is being shifted to or from the I2C Shift register. NCKI--NACK Interrupt This bit is set high when a Not Acknowledge condition is received or sent and neither the START nor the STOP bit is active. When set, this bit generates an interrupt that can only be cleared by setting the START or STOP bit, allowing the user to specify whether he wants to perform a STOP or a repeated START.
I2C Control Register
The I2C Control register enables the I2C operation.
Table 70. I2C Control Register (I2CCTL)
BITS FIELD RESET R/W ADDR
7
IEN 0 R/W
6
START 0 R/W
5
STOP 0 R/W
4
BIRQ 0 R/W F52H
3
TXI 0 R/W
2
NAK 0 R/W
1
FLUSH 0 R/W
0
FILTEN 0 R/W
IEN--I2C Enable This bit enables the I2C transmitter and receiver. START--Send Start Condition This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it sends the START condition or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if there is data in the I2C Data or I2C Shift register. If there is no data in one of these registers, the I2C Controller waits until data is loaded. If this bit is set while the I2C Controller is shifting out data, it generates a START condition after the byte shifts and the acknowledge
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phase completes. If the STOP bit is also set, it also waits until the STOP condition is sent before the START condition. STOP--Send Stop Condition This bit causes the I2C Controller to issue a Stop condition after the byte in the I2C Shift register has completed transmission or after a byte has been received in a receive operation. Once set, this bit is reset by the I2C Controller after a Stop condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register. BIRQ--Baud Rate Generator Interrupt Request This bit causes an interrupt to occur every time the baud rate generator counts down to one. This bit allows the I2C Controller to be used as an additional timer when the I2C Controller is disabled. This bit is ignored when the I2C Controller is enabled. TXI--Enable TDRE interrupts This bit enables interrupts when the I2C Data register is empty on the I2C Controller. NAK--Send NAK This bit sends a Not Acknowledge condition after the next byte of data has been read from the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is deasserted. FLUSH--Flush Data Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows flushing of the I2C Data register when an NAK is received after the data has been sent to the I2C Data register. Reading this bit always returns 0. FILTEN--I2C Signal Filter Enable Setting this bit to 1 enables low-pass digital filters on the SDA and SCL input signals. These filters reject any input pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock cycle latency on the inputs.
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator. The I2C baud rate is calculated using the following equation (note if BRG = 0x0000, use 0x10000 in the equation):
System Clock Frequency (Hz) I2C Baud Rate (bits/s) = --------------------------------------------------------------------------4 x BRG[15:0]
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.
Table 71. I2C Baud Rate High Byte Register (I2CBRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRH
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W F53H
1 R/W
1 R/W
1 R/W
1 R/W
BRH = I2C Baud Rate High Byte Most significant byte, BRG[15:8], of the I2C Baud Rate Generator's reload value.
If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH register returns the current value of the I2C Baud Rate Counter[15:8].
Table 72. I2C Baud Rate Low Byte Register (I2CBRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRL
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W F54H
1 R/W
1 R/W
1 R/W
1 R/W
BRL = I2C Baud Rate Low Byte Least significant byte, BRG[7:0], of the I2C Baud Rate Generator's reload value. Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL register returns the current value of the I2C Baud Rate Counter[7:0].
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I2C Diagnostic State Register
The I2C Diagnostic State Register provides observability of internal state. This is a read only register used for I2C diagnostics.
Table 73. I2C Diagnostic State Register (I2CDST)
BITS FIELD RESET R/W ADDR
7
SCLIN X R
6
SDAIN X R
5
STPCNT 0 R
4
3
2
TXRXSTATE 00000 R
1
0
F55H
SCLIN - Value of Serial Clock input signal SDAIN - Value of the Serial Data input signal STPCNT - Value of the internal Stop Count control signal TXRXSTATE - Value of the I2C state machine I2C Diagnostic Control Register The I2C Diagnostic Register provides control over diagnostic modes. This is a read/write register used for I2C diagnostics.
Table 74. I2C Diagnostic Control Register (I2CDIAG)
BITS FIELD RESET R/W ADDR
7
6
5
4
Reserved
3
2
1
0
DIAG
0 R
0 R
0 R
0 R F56H
0 R
0 R
0 R
0 R/W
DIAG = Diagnostic Control Bit - Selects read back value of the Baud Rate Reload registers. In diagnostic mode the Baud Rate Counter may be read back. 0 = Normal mode 1 = Diagnostic mode
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Analog-to-Digital Converter
Overview
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The features of the sigma-delta ADC include:
* * *
Five analog input sources are multiplexed with general-purpose I/O ports Interrupt upon conversion complete Internal voltage reference generator
The ADC is only available in the Z8F0822, Z8F0821, Z8F0422 and Z8F0421.
Architecture
Figure 29 illustrates the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the ADC. The ADC converts an analog input signal to its digital representation. The 5-input analog multiplexer selects one of the 5 analog input sources. The ADC requires an input reference voltage for the conversion. The voltage reference for the conversion may be input through the external VREF pin or generated internally by the voltage reference generator.
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Internal Voltage Reference Generator
VREF
Analog-to-Digital Converter IRQ Reference Input ANA0 ANA1 Analog Input ANA2 ANA3 ANA4 Analog Input Multiplexer
ANAIN[3:0]
Figure 29. Analog-to-Digital Converter Block Diagram
Operation
Automatic Power-Down
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of the ADC are automatically powered-down. From this power-down state, the ADC requires 40 system clock cycles to power-up. The ADC powers up when a conversion is requested using the ADC Control register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion are as follows:
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1. Enable the desired analog inputs by configuring the general-purpose I/O pins for alternate function. This configuration disables the digital input and output drivers. 2. Write to the ADC Control register to configure the ADC and begin the conversion. The bit fields in the ADC Control register can be written simultaneously: - Write to the ANAIN[3:0] field to select one of the 5 analog input sources. - Clear CONT to 0 to select a single-shot conversion. - Write to the VREF bit to enable or disable the internal voltage reference generator. - Set CEN to 1 to start the conversion. 3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. When the conversion is complete, the ADC control logic performs the following operations: - 10-bit data result written to {ADCDH[7:0], ADCDL[7:6]}. - CEN resets to 0 to indicate the conversion is complete. - An interrupt request is sent to the Interrupt Controller. 5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analogto-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each conversion. Caution: In CONTINUOUS mode, users must be aware that ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not seen at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency.
The steps for setting up the ADC and initiating continuous conversion are as follows: 1. Enable the desired analog input by configuring the general-purpose I/O pins for alternate function. This disables the digital input and output driver. 2. Write to the ADC Control register to configure the ADC for continuous conversion. The bit fields in the ADC Control register may be written simultaneously: - Write to the ANAIN[3:0] field to select one of the 5 analog input sources.
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- - -
Set CONT to 1 to select continuous conversion. Write to the VREF bit to enable or disable the internal voltage reference generator. Set CEN to 1 to start the conversions.
3. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: - CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation. - An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete. 4. Thereafter, the ADC writes a new 10-bit data result to {ADCDH[7:0], ADCDL[7:6]} every 256 system clock cycles. An interrupt request is sent to the Interrupt Controller when each conversion is complete. 5. To disable continuous conversion, clear the CONT bit in the ADC Control register to 0.
ADC Control Register Definitions
ADC Control Register
The ADC Control register selects the analog input channel and initiates the analog-to-digital conversion.
Table 75. ADC Control Register (ADCCTL)
BITS FIELD RESET R/W ADDR
7
CEN 0 R/W
6
Reserved 0 R/W
5
VREF 1 R/W
4
CONT 0 R/W F70H
3
2
1
0
ANAIN[3:0] 0000 R/W
CEN--Conversion Enable 0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears this bit to 0 when a conversion has been completed. 1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in progress, the conversion restarts. This bit remains 1 until the conversion is complete. Reserved--Must be 0.
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VREF 0 = Internal reference generator enabled. The VREF pin should be left unconnected or capacitively coupled to analog ground (AVSS). 1 = Internal voltage reference generator disabled. An external voltage reference must be provided through the VREF pin. CONT 0 = Single-shot conversion. ADC data is output once at completion of the 5129 system clock cycles. 1 = Continuous conversion. ADC data updated every 256 system clock cycles. ANAIN--Analog Input Select These bits select the analog input for conversion. Not all Port pins in this list are available in all packages for the Z8F082x family of products. Refer to the Signal and Pin Descriptions chapter for information regarding the Port pins available with each package style. Do not enable unavailable analog inputs. 0000 = ANA0 0001 = ANA1 0010 = ANA2 0011 = ANA3 0100 = ANA4 0101 = Reserved. 011X = Reserved. 1XXX = Reserved.
ADC Data High Byte Register
The ADC Data High Byte register contains the upper eight bits of the 10-bit ADC output. During a single-shot conversion, this value is invalid. Access to the ADC Data High Byte register is read-only. The full 10-bit ADC result is given by {ADCDH[7:0], ADCDL[7:6]}. Reading the ADC Data High Byte register latches data in the ADC Low Bits register.
Table 76. ADC Data High Byte Register (ADCDH)
BITS FIELD RESET R/W ADDR
7
6
5
4
ADCDH X R F72H
3
2
1
0
ADCDH--ADC Data High Byte This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid
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during a single-shot conversion. During a continuous conversion, the last conversion output is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Bits register contains the lower two bits of the conversion value. The data in the ADC Data Low Bits register is latched each time the ADC Data High Byte register is read. Reading this register always returns the lower two bits of the conversion last read into the ADC High Byte register. Access to the ADC Data Low Bits register is readonly. The full 10-bit ADC result is given by {ADCDH[7:0], ADCDL[7:6]}.
Table 77. ADC Data Low Bits Register (ADCDL)
BITS FIELD RESET R/W ADDR
7
ADCDL X R
6
5
4
3
Reserved X R F73H
2
1
0
ADCDL--ADC Data Low Bits These are the least significant two bits of the 10-bit ADC output. These bits are undefined after a Reset. Reserved These bits are reserved and are always undefined.
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Flash Memory
Overview
The products in the Z8F082x family feature either 4KB (4096) or 8KB (8192 bytes) of non-volatile Flash memory with read/write/erase capability. The Flash memory can be programmed and erased in-circuit by either user code or through the On-Chip Debugger. The Flash memory array is arranged in 512-byte per page. The 512-byte page is the minimum Flash block size that can be erased. The Flash memory is also divided into 8 sectors which can be protected from programming and erase operations on a per sector basis. Table 78 describes the Flash memory configuration for each device in the Z8F082x family. Table 79 lists the sector address ranges. Figure 30 illustrates the Flash memory arrangement.
Table 78. Flash Memory Configurations Number of Pages 8 16 Program Memory Addresses 0000H - 0FFFH 0000H - 1FFFH Number of Sectors 8 8 Pages per Sector 1 2
Part Number Z8F04xx Z8F08xx
Flash Size 4KB (4096) 8KB (8192)
Sector Size 0.5KB (512) 1KB (1024)
Table 79. Flash Memory Sector Addresses Flash Sector Address Ranges Sector Number 0 1 2 3 4 5 6 7 Z8F04xx 0000H-01FFH 0200H-03FFH 0400H-05FFH 0600H-07FFH 0800H-09FFH 0A00H-0BFFH 0C00H-0DFFH 0E00H-0FFFH Z8F08xx 0000H-03FFH 0400H-07FFH 0800H-0BFFH 0C00H-0FFFH 1000H-13FFH 1400H-17FFH 1800H-1BFFH 1C00H-1FFFH
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8KB Flash Program Memory Addresses 1FFFH 1E00H 1DFFH 1C00H 1BFFH 1A00H
16 Pages 512 Bytes per Page
05FFH 0400H 03FFH 0200H 01FFH 0000H
Figure 30. Flash Memory Arrangement
Information Area
Table 80 describes the Z8F082x family Information Area. This 512-byte Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When access is enabled, the Information Area is mapped into Program Memory and overlays the 512 bytes at addresses FE00H to FFFFH. When the Information Area access is enabled, LDC instructions return data from the Information Area. CPU instruction fetches always comes from
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Program Memory regardless of the Information Area access bit. Access to the Information Area is read-only.
Table 80. Z8F082x family Information Area Map Program Memory Address (Hex) FE00H-FE3FH FE40H-FE53H Function Reserved Part Number 20-character ASCII alphanumeric code Left justified and filled with zeros Reserved
FE54H-FFFFH
Operation
The Flash Controller provides the proper signals and timing for Byte Programming, Page Erase, and Mass Erase of the Flash memory. The Flash Controller contains a protection mechanism, via the Flash Control register (FCTL), to prevent accidental programming or erasure. The following subsections provide details on the various operations (Lock, Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase).
Timing Using the Flash Frequency Registers
Before performing a program or erase operation on the Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasure of the Flash with system clock frequencies ranging from 20kHz through 20MHz (the valid range is limited to the device operating frequencies). The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Frequency value must contain the system clock frequency in kHz. This value is calculated using the following equation:.
System Clock Frequency (Hz) FFREQ[15:0] = --------------------------------------------------------------------------1000
Caution: Flash programming and erasure are not supported for system clock frequencies below 20kHz, above 20MHz, or outside of the device operating frequency range. The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper Flash programming and erase operations.
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Flash Read Protection
The user code contained within the Flash memory can be protected from external access. Programming the Flash Read Protect Option Bit prevents reading of user code by the OnChip Debugger or by using the Flash Controller Bypass mode. Refer to the Option Bits chapter and the On-Chip Debugger chapter for more information.
Flash Write/Erase Protection
The Z8F082x family provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by the Flash Controller unlock mechanism, the Flash Sector Protect register, and the Flash Write Protect option bit. Flash Controller Unlock Mechanism At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash memory. To program or erase the Flash memory, the Flash controller must be unlocked. After unlocking the Flash Controller, the Flash can be programmed or erased. Any value written by user code to the Flash Control register or Flash Page Select Register out of sequence will lock the Flash Controller. The proper steps to unlock the Flash Controller from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page to be programmed or erased to the Flash Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Flash Page Select register. Flash Sector Protection The Flash Sector Protect register can be configured to prevent sectors from being programmed or erased. Once a sector is protected, it cannot be unprotected by user code. The Flash Sector Protect register will be cleared after reset and any previously written protection values will be lost. User code should write this register in their initialization routine if they want to enable sector protection. The Flash Sector Protect register shares its Register File address with the Flash Page Select register. The Flash Sector Protect register is accessed by writing the Flash Control register with 5EH. Once the Flash Sector Protect register is selected, it can be accessed at the Flash Page Select Register address. When user code writes the Flash Sector Protect register, bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5EH to the Flash Control register will de-select the Flash Sector Protect register and re-enable access to the Flash Page Select register.
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The proper steps to setup the Flash Sector Protect register from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write 5EH to the Flash Control register to select the Flash Sector Protect register. 3. Read and/or write the Flash Sector Protect register which is now at Register File address FF9H. 4. Write 00H to the Flash Control register to return the Flash Controller to its reset state. Flash Write Protection Option Bit The Flash Write Protect option bit can be enabled to block all program and erase operations from user code. Refer to the Option Bits chapter for more information.
Byte Programming
When the Flash Controller is unlocked, writes to Program Memory from user code will program a byte into the Flash if the address is located in the unlocked page. An erased Flash byte contains all ones (FFH). The programming operation can only be used to change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page Erase or Mass Erase operation. Byte Programming can be accomplished using the eZ8 CPU's LDC or LDCI instructions. Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Interrupts that occur when a Programming operation is in progress will be serviced once the Programming operation is complete. To exit Programming mode and lock the Flash Controller, write 00H to the Flash Control register. User code cannot program Flash Memory on a page that lies in a protected sector. When user code writes memory locations, only addresses located in the unlocked page will be programmed. Memory writes outside of the unlocked page are ignored. Caution: Each memory location should not be programmed more than twice before an erase occurs.
The proper steps to program the Flash from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page of memory to be programmed to the Flash Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Flash Page Select register.
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6. Write Program Memory using LDC or LDCI instructions to program the Flash. 7. Repeat step 6 to program additional memory locations on the same page. 8. Write 00H to the Flash Control register to lock the Flash Controller.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Flash Page Select register identifies the page to be erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. Interrupts that occur when the Page Erase opertion is in progress will be serviced once the Page Erase operation is complete. When the Page Erase operation is complete, the Flash Controller returns to its locked state. Only pages located in unprotected sectors can be erased. The proper steps to perform a Page Erase operation are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page to be erased to the Flash Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Flash Page Select register. 6. Write the Page Erase command 95H to the Flash Control register.
Mass Erase
The Flash memory cannot be Mass Erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming algorithms by controlling the Flash programming signals directly. Flash Controller Bypass is recommended for gang programming applications and large volume customers who do not require in-circuit programming of the Flash memory. Please refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!TM for more information on bypassing the Flash Controller. This document is available for download at www.zilog.com.
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Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the On-Chip Debugger:
* * * * * * *
The Flash Write Protect option bit is ignored. The Flash Sector Protect register is ignored for programming and erase operations. Programming operations are not limited to the page selected in the Flash Page Select register. Bits in the Flash Sector Protect register can be written to one or zero. The second write of the Flash Page Select register to unlock the Flash Controller is not necessary. The Flash Page Select register can be written when the Flash Controller is unlocked. The Mass Erase command is enabled.
Flash Control Register Definitions
Flash Control Register
The Flash Control register is used to unlock the Flash Controller for programming and erase operations, or to select the Flash Sector Protect register. The Write-only Flash Control Register shares its Register File address with the Read-only Flash Status Register.
Table 81. Flash Control Register (FCTL)
BITS FIELD RESET R/W ADDR
7
6
5
4
FCMD
3
2
1
0
0 W
0 W
0 W
0 W FF8H
0 W
0 W
0 W
0 W
FCMD--Flash Command 73H = First unlock command. 8CH = Second unlock command. 95H = Page erase command. 63H = Mass erase command 5EH = Flash Sector Protect register select. * All other commands, or any command out of sequence, will lock the Flash Controller.
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Flash Status Register
The Flash Status register indicates the current state of the Flash Controller. This register can be read at any time. The Read-only Flash Status Register shares its Register File address with the Write-only Flash Control Register.
Table 82. Flash Status Register (FSTAT)
BITS FIELD RESET R/W ADDR
7
Reserved 0 R
6
5
4
3
FSTAT
2
1
0
0 R
0 R
0 R FF8H
0 R
0 R
0 R
0 R
Reserved These bits are reserved and must be 0. FSTAT--Flash Controller Status 00_0000 = Flash Controller locked. 00_0001 = First unlock command received. 00_0010 = Second unlock command received. 00_0011 = Flash Controller unlocked. 00_0100 = Flash Sector Protect register selected. 00_1xxx = Program operation in progress. 01_0xxx = Page erase operation in progress. 10_0xxx = Mass erase operation in progress.
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Flash Page Select Register
The Flash Page Select (FPS) register selects the Flash memory page to be erased or programmed. Each Flash Page contains 512 bytes of Flash memory. During a Page Erase operation, all Flash memory locations with the 7 most significant bits of the address given by the PAGE field will be erased to FFH. The Flash Page Select register shares its Register File address with the Flash Sector Protect Register. The Flash Page Select register cannot be accessed when the Flash Sector Protect register is enabled.
Table 83. Flash Page Select Register (FPS)
BITS FIELD RESET R/W ADDR
7
INFO_EN 0 R/W
6
5
4
3
PAGE
2
1
0
0 R/W
0 R/W
0 R/W FF9H
0 R/W
0 R/W
0 R/W
0 R/W
INFO_EN--Information Area Enable 0 = Information Area is not selected. 1 = Information Area is selected. The Information area is mapped into the Program Memory address space at addresses FE00H through FFFFH. PAGE--Page Select This 7-bit field selects the Flash memory page for Programming and Page Erase operations. Program Memory Address[15:9] = PAGE[6:0].
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Flash Sector Protect Register
The Flash Sector Protect register protects Flash memory sectors from being programmed or erased from user code. The Flash Sector Protect register shares its Register File address with the Flash Page Select register. The Flash Sector protect register can be accessed only after writing the Flash Control register with 5EH. User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).
Table 84. Flash Sector Protect Register (FPROT)
BITS FIELD RESET R/W ADDR
7
SECT7 0 R/W1
6
SECT6 0 R/W1
5
SECT5 0 R/W1
4
SECT4 0 R/W1 FF9H
3
SECT3 0 R/W1
2
SECT2 0 R/W1
1
SECT1 0 R/W1
0
SECT0 0 R/W1
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).
SECTn--Sector Protect 0 = Sector n can be programmed or erased from user code. 1 = Sector n is protected and cannot be programmed or erased from user code. * User code can only write bits from 0 to 1.
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Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Frequency registers should be written with the system clock frequency in kHz for Program and Erase operations. The Flash Frequency value is calculated using the following equation:
FFREQ[15:0] = { FFREQH[7:0],FFREQL[7:0] } = System Clock Frequency -------------------------------------------------------------1000
Caution: Flash programming and erasure is not supported for system clock frequencies below 20kHz, above 20MHz, or outside of the valid operating frequency range for the device. The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper program and erase times.
Table 85. Flash Frequency High Byte Register (FFREQH)
BITS FIELD RESET R/W ADDR
7
6
5
4
FFREQH
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W FFAH
0 R/W
0 R/W
0 R/W
0 R/W
Table 86. Flash Frequency Low Byte Register (FFREQL)
BITS FIELD RESET R/W ADDR
7
6
5
4
FFREQL
3
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W FFBH
0 R/W
0 R/W
0 R/W
0 R/W
FFREQH and FFREQL--Flash Frequency High and Low Bytes These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
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Option Bits
Overview
Option Bits allow user configuration of certain aspects of Z8F082x family operation. The feature configuration data is stored in Program Memory and read during Reset. The features available for control through the Option Bits are:
* * * * * *
Watch-Dog Timer time-out response selection-interrupt or Reset. Watch-Dog Timer enabled at Reset. The ability to prevent unwanted read access to user code in Program Memory. The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory. Voltage Brown-Out configuration-always enabled or disabled during STOP mode to reduce STOP mode power consumption. Oscillator mode selection-for high, medium, and low power crystal oscillators, or external RC oscillator.
Operation
Option Bit Configuration By Reset
Each time the Option Bits are programmed or erased, the device must be Reset for the change to take place. During any reset operation (System Reset, Reset, or STOP Mode Recovery), the Option Bits are automatically read from the Program Memory and written to Option Configuration registers. The Option Configuration registers control operation of the devices within the Z8F082x family. Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access.
Option Bit Address Space
The first two bytes of Program Memory at addresses 0000H and 0001H are reserved for the user programmable Option Bits. The byte at Program Memory address 0000H configures user options. The byte at Program Memory address 0001H is reserved for future use and must be left in its unprogrammed state.
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Program Memory Address 0000H
Table 87. Option Bits At Program Memory Address 0000H
BITS
7
6
5
4
3
VBO_AO U R/W
2
RP
1
FHSWP
0
FWP
FIELD WDT_RES WDT_AO RESET R/W ADDR
OSC_SEL[1:0]
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES--Watch-Dog Timer Reset 0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request. 1 = Watch-Dog Timer time-out causes a Reset. This setting is the default for unprogrammed (erased) Flash. WDT_AO--Watch-Dog Timer Always On 0 = Watch-Dog Timer is automatically enabled upon application of system power. WatchDog Timer can not be disabled. 1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled, the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This setting is the default for unprogrammed (erased) Flash. OSC_SEL[1:0]--Oscillator Mode Selection 00 = On-chip oscillator configured for use with external RC networks (<4MHz). 01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). 10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz). 11 = Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz). This setting is the default for unprogrammed (erased) Flash. VBO_AO--Voltage Brown-Out Protection Always On 0 = Voltage Brown-Out Protection is disabled in STOP mode to reduce total power consumption. 1 = Voltage Brown-Out Protection is always enabled including during STOP mode. This setting is the default for unprogrammed (erased) Flash. RP--Read Protect 0 = User program code is inaccessible. Limited control features are available through the On-Chip Debugger. 1 = User program code is accessible. All On-Chip Debugger commands are enabled. This setting is the default for unprogrammed (erased) Flash.
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FHSWP--Flash High Sector Write Protect FWP--Flash Write Protect These two Option Bits combine to provide 3 levels of Program Memory protection:
FHSWP 0 FWP 0 Description Programming and erasure disabled for all of Program Memory. Programming, Page Erase, and Mass Erase via User Code is disabled. Mass Erase is available through the On-Chip Debugger. Programming and Page Erase are enabled for the High Sector of the Program Memory only. The High Sector on the Z8F082x family products contains 512 to 1024 Bytes of Flash with addresses at the top of the available Flash memory. Programming and Page Erase are disabled for the other portions of the Program Memory. Mass erase through user code is disabled. Mass Erase is available through the On-Chip Debugger. Programming, Page Erase, and Mass Erase are enabled for all of Program Memory.
1
0
0 or 1
1
Program Memory Address 0001H
Table 88. Options Bits at Program Memory Address 0001H
BITS FIELD RESET R/W ADDR
7
6
5
4
Reserved U R/W
3
2
1
0
Program Memory 0001H
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved These Option Bits are reserved for future use and must always be 1. This setting is the default for unprogrammed (erased) Flash.
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On-Chip Debugger
Overview
The Z8F082x family products have an integrated On-Chip Debugger (OCD) that provides advanced debugging features including:
* * * * Architecture
Reading and writing of the Register File Reading and writing of Program and Data Memory Setting of Breakpoints Execution of eZ8 CPU instructions.
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver, auto-baud generator, and debug controller. Figure 31 illustrates the architecture of the OnChip Debugger
System Clock
Auto-Baud Detector/Generator eZ8 CPU Control Transmitter Debug Controller
DBG Pin Receiver
Figure 31. On-Chip Debugger Block Diagram
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Operation
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bi-directional open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS-232. This pin can interface the Z8F082x family products to the serial port of a host PC using minimal external hardware.Two different methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 32 and 33. Caution: For operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be supplied with power, and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must always be connected to VDD through an external pull-up resistor to insure proper operation.
VDD RS-232 Transceiver Diode RS-232 TX DBG Pin
10K Ohm
RS-232 RX
Figure 32. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1)
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VDD RS-232 Transceiver RS-232 TX
Open-Drain Buffer
10K Ohm DBG Pin
RS-232 RX
Figure 33. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2)
Debug Mode
The operating characteristics of the Z8F082x family devices in DEBUG mode are:
* * * * *
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions. The system clock operates unless in STOP mode. All enabled on-chip peripherals operate unless in STOP mode. Automatically exits HALT mode. Constantly refreshes the Watch-Dog Timer, if enabled.
Entering Debug Mode The device enters DEBUG mode following any of the following operations:
* * * * *
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface. eZ8 CPU execution of a BRK (Breakpoint) instruction. Match of PC to OCDCNTR register (when enabled) OCDCNTR register decrements to 0000H (when enabled) If the DBG pin is Low when the device exits Reset, the On-Chip Debugger automatically puts the device into DEBUG mode.
Exiting Debug Mode The device exits DEBUG mode following any of the following operations:
*
Clearing the DBGMODE bit in the OCD Control Register to 0.
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* * * *
Power-on reset Voltage Brown-out reset Asserting the RESET pin Low to initiate a Reset. Driving the DBG pin Low while the device is in STOP mode initiates a System Reset.
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit (Figure 34)
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
Figure 34. OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (bits per second) with various system clock frequencies, the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is idle until it receives data. The OCD requires that the first character sent from the host is the character 80H. The character 80H has eight continuous bits Low (one Start bit plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly. The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud rate is the system clock frequency divided by 512. For optimal operation, the maximum recommended baud rate is the system clock frequency divided by 8. The theoretical maximum baud rate is the system clock frequency divided by 4. This theoretical maximum is possible for low noise designs with clean signals. Table 89 lists minimum and recommended maximum baud rates for sample crystal frequencies.
Table 89. OCD Baud-Rate Limits System Clock Frequency (MHz) 20.0 1.0 0.032768 (32KHz) Recommended Maximum Baud Rate (kbits/s) 2500 125.0 4.096 Minimum Baud Rate (kbits/s) 39.1 1.96 0.064
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If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured by sending 80H.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
* * *
Serial Break (a minimum of nine continuous bits Low) Framing Error (received Stop bit is Low) Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress, transmits a Serial Break 4096 System Clock cycles long back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host should transmit a Serial Break on the DBG pin when first connecting to the Z8F082x family device or when recovering from an error. A Serial Break from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Control register. A Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character.
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD idles the eZ8 CPU and enters Debug Mode. If Breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP. If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK instruction, then the CPU is still enabled to service DMA and interrupt requests. The loop on BRK instruction can be used to service interrupts in the background. For interrupts to be serviced in the background, there cannot be any breakpoints in the interrupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts to be serviced in the background, interrupts must also be enabled. Debugging software should not automatically enable interrupts when using this feature, since interrupts are typically disabled during critical sections of code where interrupts should not occur (such as adjusting the stack pointer or modifying shared data).
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Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is looping on a BRK instruction. When software wants to stop the CPU on the BRK instruction it is looping on, software should not set the DBGMODE bit of the OCDCTL register. The CPU may have vectored to and be in the middle of an interrupt service routine when this bit gets set. Instead, software should clear the BRKLP bit. This allows the CPU to finish the interrupt service routine it may be in and return the BRK instruction. When the CPU returns to the BRK instruction it was previously looping on, it automatically sets the DBGMODE bit and enter DEBUG mode. Software should also note that the majority of the OCD commands are still disabled when the eZ8 CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part must be in DEBUG mode before these commands can be issued. Breakpoints in Flash Memory The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a byte in Flash memory. To implement a Breakpoint, write 00H to the desired address, overwriting the current instruction. To remove a Breakpoint, the corresponding page of Flash memory must be erased and reprogrammed with the original data.
OCDCNTR Register
The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used for the following:
* * *
Count system clock cycles between Breakpoints. Generate a BRK when it counts down to zero. Generate a BRK when its value matches the Program Counter.
When configured as a counter, the OCDCNTR register starts counting when the On-Chip Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches the maximum count of FFFFH. The OCDCNTR register automatically resets itself to 0000H when the OCD exits DEBUG mode if it is configured to count clock cycles between breakpoints. Caution: The OCDCNTR register is used by many of the OCD commands. It counts the number of bytes for the register and memory read/write commands. It holds the residual value when generating the CRC. Therefore, if the OCDCNTR is being used to generate a BRK, its value should be written as a last step before leaving DEBUG mode.
Since this register is overwritten by various OCD commands, it should only be used to generate temporary breakpoints, such as stepping over CALL instructions or running to a specific instruction and stopping.
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On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are available. In DEBUG mode, all OCD commands become available unless the user code and control registers are protected by programming the Read Protect Option Bit (RP). The Read Protect Option Bit prevents the code in memory from being read out of the Z8F082x family products. When this option is enabled, several of the OCD commands are disabled. Table 90 contains a summary of the On-Chip Debugger commands. Each OCD command is described in further detail in the bulleted list following Table 90. Table 90 indicates those commands that operate when the device is not in DEBUG mode (normal operation) and those commands that are disabled by programming the Read Protect Option Bit.
Table 90. On-Chip Debugger Commands Enabled when NOT in DEBUG mode? Yes Yes Yes Yes Disabled by Read Protect Option Bit Cannot clear DBGMODE bit Disabled Disabled Only writes of the Flash Memory Control registers are allowed. Additionally, only the Mass Erase command is allowed to be written to the Flash Control register. Disabled Disabled Disabled Yes Disabled
Debug Command Read OCD Revision Write OCD Counter Register Read OCD Status Register Read OCD Counter Register Write OCD Control Register Read OCD Control Register Write Program Counter Read Program Counter Write Register
Command Byte 00H 01H 02H 03H 04H 05H 06H 07H 08H
Read Register Write Program Memory Read Program Memory Write Data Memory Read Data Memory Read Program Memory CRC Reserved Step Instruction
09H 0AH 0BH 0CH 0DH 0EH 0FH 10H
-
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Table 90. On-Chip Debugger Commands Enabled when NOT in DEBUG mode? Disabled by Read Protect Option Bit Disabled Disabled -
Debug Command Stuff Instruction Execute Instruction Reserved
Command Byte 11H 12H 13H - FFH
In the following bulleted list of OCD Commands, data and commands sent from the host to the On-Chip Debugger are identified by 'DBG Command/Data'. Data sent from the On-Chip Debugger back to the host is identified by 'DBG Data'
*
Read OCD Revision (00H)--The Read OCD Revision command determines the version of the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision number changes.
DBG 00H DBG OCDREV[15:8] (Major revision number) DBG OCDREV[7:0] (Minor revision number)
*
Write OCD Counter Register (01H)--The Write OCD Counter Register command writes the data that follows to the OCDCNTR register. If the device is not in DEBUG mode, the data is discarded.
DBG 01H DBG OCDCNTR[15:8] DBG OCDCNTR[7:0]
*
Read OCD Status Register (02H)--The Read OCD Status Register command reads the OCDSTAT register.
DBG 02H DBG OCDSTAT[7:0]
*
Read OCD Counter Register (03H)--The OCD Counter Register can be used to count system clock cycles in between Breakpoints, generate a BRK when it counts down to zero, or generate a BRK when its value matches the Program Counter. Since this register is really a down counter, the returned value is inverted when this register is read so the returned result appears to be an up counter. If the device is not in DEBUG mode, this command returns FFFFH.
DBG 03H DBG ~OCDCNTR[15:8] DBG ~OCDCNTR[7:0]
*
Write OCD Control Register (04H)--The Write OCD Control Register command writes the data that follows to the OCDCTL register. When the Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be
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cleared to 0 and the only method of putting the device back into normal operating mode is to reset the device.
DBG 04H DBG OCDCTL[7:0]
*
Read OCD Control Register (05H)--The Read OCD Control Register command reads the value of the OCDCTL register.
DBG 05H DBG OCDCTL[7:0]
*
Write Program Counter (06H)--The Write Program Counter command writes the data that follows to the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the Program Counter (PC) values are discarded.
DBG 06H DBG ProgramCounter[15:8] DBG ProgramCounter[7:0]
*
Read Program Counter (07H)--The Read Program Counter command reads the value in the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFFFH.
DBG 07H DBG ProgramCounter[15:8] DBG ProgramCounter[7:0]
*
Write Register (08H)--The Write Register command writes data to the Register File. Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If the device is not in DEBUG mode, the address and data values are discarded. If the Read Protect Option Bit is enabled, then only writes to the Flash Control Registers are allowed and all other register write data values are discarded.
DBG DBG DBG DBG DBG 08H {4'h0,Register Address[11:8]} Register Address[7:0] Size[7:0] 1-256 data bytes
*
Read Register (09H)--The Read Register command reads data from the Register File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for all the data values.
DBG DBG DBG DBG DBG 09H {4'h0,Register Address[11:8] Register Address[7:0] Size[7:0] 1-256 data bytes
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*
Write Program Memory (0AH)--The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). The on-chip Flash Controller must be written to and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded.
DBG DBG DBG DBG DBG DBG 0AH Program Memory Address[15:8] Program Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Program Memory (0BH)--The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for the data.
DBG DBG DBG DBG DBG DBG 0BH Program Memory Address[15:8] Program Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Write Data Memory (0CH)--The Write Data Memory command writes data to Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded.
DBG DBG DBG DBG DBG DBG 0CH Data Memory Address[15:8] Data Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Data Memory (0DH)--The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG mode, this command returns FFH for the data.
DBG DBG DBG DBG 0DH Data Memory Address[15:8] Data Memory Address[7:0] Size[15:8]
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DBG Size[7:0] DBG 1-65536 data bytes
*
Read Program Memory CRC (0EH)--The Read Program Memory CRC command computes and returns the CRC (cyclic redundancy check) of Program Memory using the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory.
DBG 0EH DBG CRC[15:8] DBG CRC[7:0]
*
Step Instruction (10H)--The Step Instruction command steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command.
DBG 10H
*
Stuff Instruction (11H)--The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command.
DBG 11H DBG opcode[7:0]
*
Execute Instruction (12H)--The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over Breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command
DBG 12H DBG 1-5 byte opcode
On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register controls the state of the On-Chip Debugger. This register enters or exits DEBUG mode and enables the BRK instruction. It can also reset the Z8F082x family device.
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A "reset and stop" function can be achieved by writing 81H to this register. A "reset and go" function can be achieved by writing 41H to this register. If the device is in DEBUG mode, a "run" function can be implemented by writing 40H to this register.
Table 91. OCD Control Register (OCDCTL)
BITS
7
6
BRKEN 0 R/W
5
4
3
BRKPC 0 R
2
BRKZRO 0 R
1
Reserved 0 R
0
RST 0 R/W
FIELD DBGMODE RESET R/W
0 R/W
DBGACK BRKLOOP 0 R/W 0 R
DBGMODE--Debug Mode Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, the eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start running again. This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the Read Protect Option Bit is enabled, this bit can only be cleared by resetting the device, it cannot be written to 0. 0 = The Z8F082x family device is operating in NORMAL mode. 1 = The Z8F082x family device is in DEBUG mode. BRKEN--Breakpoint Enable This bit controls the behavior of the BRK instruction (opcode 00H). By default, Breakpoints are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit. 0 = BRK instruction is disabled. 1 = BRK instruction is enabled. DBGACK--Debug Acknowledge This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends an Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. BRKLOOP--Breakpoint Loop This bit determines what action the OCD takes when a BRK instruction is decoded if breakpoints are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automatically set to 1 and the OCD enterd DEBUG mode. If BRKLOOP is set to 1, then the eZ8 CPU loops on the BRK instruction. 0 = BRK instruction sets DBGMODE to 1. 1 = eZ8 CPU loops on BRK instruction. BRKPC--Break when PC == OCDCNTR If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
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matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is running. 0 = OCDCNTR is setup as counter 1 = OCDCNTR generates hardware break when PC == OCDCNTR BRKZRO--Break when OCDCNTR == 0000H If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCDCNTR register counts down to 0000H. If this bit is set, the OCDCNTR register is not reset when the part leaves DEBUG Mode. 0 = OCD does not generate BRK when OCDCNTR decrements to 0000H 1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000H Reserved These bits are reserved and must be 0. RST--Reset Setting this bit to 1 resets the Z8F082x family device. The device goes through a normal Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is automatically cleared to 0 when the reset finishes. 0 = No effect. 1 = Reset the Z8F082x family device.
OCD Status Register
The OCD Status register reports status information about the current state of the debugger and the system.
Table 92. OCD Status Register (OCDSTAT)
BITS FIELD RESET R/W
7
IDLE 0 R
6
HALT 0 R
5
RPEN 0 R
4
3
2
Reserved
1
0
0 R
0 R
0 R
0 R
0 R
IDLE--CPU idling This bit is set if the part is in DEBUG mode (DBGMODE is 1), or if a BRK instruction occurred since the last time OCDCTL was written. This can be used to determine if the CPU is running or if it is idling. 0 = The eZ8 CPU is running. 1 = The eZ8 CPU is either stopped or looping on a BRK instruction. HALT--HALT Mode 0 = The device is not in HALT mode. 1 = The device is in HALT mode.
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RPEN--Read Protect Option Bit Enabled 0 = The Read Protect Option Bit is disabled (1). 1 = The Read Protect Option Bit is enabled (0), disabling many OCD commands. Reserved. Must be 0.
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On-Chip Oscillator
Overview
The products in the Z8F082x family feature an on-chip oscillator for use with external crystals with frequencies from 32KHz to 20MHz. In addition, the oscillator can support external RC networks with oscillation frequencies up to 4MHz or ceramic resonators with frequencies up to 20MHz. This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32kHz-20MHz). If an external clock generator is used, the XOUT pin must be left unconnected. When configured for use with crystal oscillators or external clock drivers, the frequency of the signal on the XIN input pin determines the frequency of the system clock (that is, no internal clock divider). In RC operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle.
Operating Modes
The Z8F082x family products support four different oscillator modes:
* * * *
On-chip oscillator configured for use with external RC networks (<4MHz). Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz). Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz to 20.0MHz).
The oscillator mode is selected using user-programmable Option Bits. Please refer to the Option Bits chapter for information.
Crystal Oscillator Operation
Figure 35 illustrates a recommended configuration for connection with an external fundamental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crystal specifications are provided in Table 93. Resistor R1 is optional and limits total power dissipation by the crystal. Printed circuit board layout should add no more than 4pF of
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stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
R1 = 220 Crystal
C1 = 22pF
C2 = 22pF
Figure 35. Recommended 20MHz Crystal Oscillator Configuration
Table 93. Recommended Crystal Oscillator Specifications (20MHz Operation) Parameter Frequency Resonance Mode Series Resistance (RS) Load Capacitance (CL) Shunt Capacitance (C0) Drive Level Value 20 Parallel Fundamental 25 20 7 1 W pF pF mW Maximum Maximum Maximum Maximum Units MHz Comments
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Oscillator Operation with an External RC Network
Figure 36 illustrates a recommended configuration for connection with an external resistor-capacitor (RC) network.
VDD
R
XIN
C
Figure 36. Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 15k is recommended for oscillator operation with an external RC network. The minimum resistance value to ensure operation is 10k. The typical oscillator frequency can be estimated from the values of the resistor (R in k) and capacitor (C in pF) elements using the following equation:
1 x10 Oscillator Frequency (kHz) = ------------------------------( 1.5 x R x C )
Figure 37 illustrates the typical (3.3V and 250C) oscillator frequency as a function of the capacitor (C in pF) employed in the RC network assuming a 15k external resistor. For very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed circuit board should be included in the estimation of the oscillator frequency.
6
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1000 900 800 700 600
F (kHz)
500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000
C (pF)
Figure 37. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 15k Resistor
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Electrical Characteristics
All data in this chapter is pre-qualification and pre-characterization and is subject to change.
Absolute Maximum Ratings
Caution: Stresses greater than those listed in Table 94 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or VSS).
Table 94. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS Voltage on AVSS pin with respect to VSS Voltage on VDD pin with respect to VSS Voltage on AVDD pin with respect to VDD Maximum current on input and/or inactive output pin Maximum output current from active output pin 20-pin SSOP Package Maximum Ratings at 0 C to 70 C Total power dissipation Maximum current into VDD or out of VSS 430 120 mW mA
0 0
Minimum Maximum -40 -65 -0.3 -0.3 -0.3 -0.3 -5 -25 +105 +150 +5.5 +0.3 +3.6 +0.3 +5 +25
Units C C V V V V A mA
Notes 1
2 2
Notes: 1. This voltage applies to all pins except the following: VDD, AVDD, VREF, pins supporting analog input (Port B), and where noted otherwise.
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Table 94. Absolute Maximum Ratings (Continued) Parameter 20-pin SSOP Package Maximum Ratings at Total power dissipation Maximum current into VDD or out of VSS 20-pin PDIP Package Maximum Ratings at 00C to 700C Total power dissipation Maximum current into VDD or out of VSS 20-pin PDIP Package Maximum Ratings at Total power dissipation Maximum current into VDD or out of VSS 28-pin SOIC Package Maximum Ratings at 00C to 700C Total power dissipation Maximum current into VDD or out of VSS 28-pin SOIC Package Maximum Ratings at Total power dissipation Maximum current into VDD or out of VSS 28-pin PDIP Package Maximum Ratings at 00C to 700C Total power dissipation Maximum current into VDD or out of VSS 28-pin PDIP Package Maximum Ratings at 70 C to 105 C Total power dissipation Maximum current into VDD or out of VSS 400 110 mW mA
0 0
Minimum Maximum 700C to 1050C 250 69
Units
Notes
mW mA
775 215 700C to 1050C 285 79
mW mA
mW mA
450 125 700C to 1050C 260 73
mW mA
mW mA
1100 305
mW mA
Notes: 1. This voltage applies to all pins except the following: VDD, AVDD, VREF, pins supporting analog input (Port B), and where noted otherwise.
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DC Characteristics
Table 95 lists the DC characteristics of the Z8F082x family products. All voltages are referenced to VSS, the primary system ground.
Table 95. DC Characteristics TA = -400C to 1050C Symbol Parameter VDD VIL1 VIL2 VIH1 Supply Voltage Low Level Input Voltage Low Level Input Voltage High Level Input Voltage Minimum Typical Maximum Units Conditions 2.7 -0.3 -0.3 0.7*VDD - - - - 3.6 0.3*VDD 0.2*VDD 5.5 V V V V For all input pins except RESET, DBG, and XIN. For RESET, DBG, and XIN. Ports A and C pins when their programmable pull-ups are disabled. Port B pins. RESET, DBG, and XIN pins. IOL = 2mA; VDD = 3.0V High Output Drive disabled. IOH = -2mA; VDD = 3.0V High Output Drive disabled. IOL = 20mA; VDD = 3.3V High Output Drive enabled TA = -400C to +700C IOH = -20mA; VDD = 3.3V High Output Drive enabled; TA = -400C to +700C IOL = 15mA; VDD = 3.3V High Output Drive enabled; TA = +700C to +1050C IOH = 15mA; VDD = 3.3V High Output Drive enabled; TA = +700C to +1050C
VIH2 VIH3 VOL1 VOH1 VOL2
High Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage High Drive High Level Output Voltage High Drive Low Level Output Voltage High Drive High Level Output Voltage High Drive Input Leakage Current Tri-State Leakage Current GPIO Port Pad Capacitance XIN Pad Capacitance
0.7*VDD 0.8*VDD - 2.4 -
- - - - -
VDD+0.3 VDD+0.3 0.4 - 0.6
V V V V V
VOH2
2.4
-
-
V
VOL3
-
-
0.6
V
VOH3
2.4
-
-
V
IIL ITL CPAD CXIN
-5 -5 - -
- - 8.0
2
+5 +5 - -
A VDD = 3.6V; VIN = VDD or VSS1 A VDD = 3.6V pF pF
8.02
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Table 95. DC Characteristics TA = -400C to 1050C Symbol Parameter CXOUT XOUT Pad Capacitance IPU1 IPU2 ICCS1 ICCS2 ICCS3 Weak Pull-up Current Weak Pull-up Current Supply Current in Stop Mode with VBO Enabled Supply Current in Stop Mode with VBO Disabled Supply Current in Stop Mode with VBO and WDT disabled Minimum Typical Maximum Units Conditions - 9 7 9.52 20 20 600 2 1 - 50 75 pF A VDD = 2.7 - 3.6V. TA = 00C to +700C A VDD = 2.7 - 3.6V. TA = -400C to +1050C A VDD = 2.7V; 250C A VDD = 2.7V; 250C A VDD = 2.7V; 250C
1 2
This condition excludes all pins that have on-chip pull-ups, when driven Low. These values are provided for design guidance only and are not tested in production.
Figure 38 illustrates the typical current consumption while operating at 25C, 3.3V, versus the system clock frequency.
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stics
Figure 38. ICC Versus System Clock Frequency
Figure 39 illustrates the typical current consumption in HALT mode while operating at 25C, 3.3V, versus the system clock frequency.
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stics
Figure 39. ICC Versus System Clock Frequency
AC Characteristics
The section provides information on the AC characteristics and timing. All AC timing information assumes a standard load of 50pF on all outputs.
Table 96. AC Characteristics VDD = 2.7 - 3.6V TA = 00C to 700C Symbol Fsysclk Parameter System Clock Frequency Minimum Maximum - 0.032768 FXTAL Crystal Oscillator Frequency 0.032768 20.0 20.0 20.0 Units MHz MHz MHz Conditions Read-only from Flash memory. Program or erasure of the Flash memory. System clock frequencies below the crystal oscillator minimum require an external clock driver. TCLK = 1/Fsysclk TCLK = 50ns
TXIN TXINH
System Clock Period System Clock High Time
50 20
- 30
ns ns
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Table 96. AC Characteristics (Continued) VDD = 2.7 - 3.6V TA = 00C to 700C Symbol TXINL TXINR TXINF Parameter System Clock Low Time System Clock Rise Time System Clock Fall Time Minimum Maximum 20 - - 30 3 3 Units ns ns ns Conditions TCLK = 50ns TCLK = 50ns TCLK = 50ns
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On-Chip Peripheral AC and DC Electrical Characteristics
Table 97. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing TA = -400C to 1050C Symbol Parameter VPOR VVBO Power-On Reset Voltage Threshold Voltage Brown-Out Reset Voltage Threshold VPOR to VVBO hysteresis Starting VDD voltage to ensure valid Power-On Reset. TANA TPOR Power-On Reset Analog Delay Power-On Reset Digital Delay Voltage Brown-Out Pulse Rejection Period Minimum Typical1 Maximum 2.15 2.05 50 - 2.40 2.30 100 VSS 2.60 2.55 - - Units V V mV V Conditions VDD = VPOR VDD = VVBO
- -
50 10.2
- -
s ms
VDD > VPOR; TPOR Digital Reset delay follows TANA 512 WDT Oscillator cycles (50KHz) + 70 System Clock cycles (20MHz) VDD < VVBO to generate a Reset.
TVBO
- 0.10
10 -
- 100
s ms
TRAMP Time for VDD to transition from VSS to VPOR to ensure valid Reset
1 Data in the typical column is from characterization at 3.3V and 00C. These values are provided for design guidance only and are not tested in production.
Table 98. Flash Memory Electrical Characteristics and Timing VDD = 2.7 - 3.6V TA = -400C to 1050C Parameter Flash Byte Read Time Flash Byte Program Time Flash Page Erase Time Flash Mass Erase Time Minimum Typical 50 20 10 200 - - - - Maximum - 40 - - Units s s ms ms Notes
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Table 98. Flash Memory Electrical Characteristics and Timing (Continued) VDD = 2.7 - 3.6V TA = -400C to 1050C Parameter Writes to Single Address Before Next Erase Flash Row Program Time Minimum Typical - - - - Maximum 2 8 ms Cumulative program time for single row cannot exceed limit before next erase. This parameter is only an issue when bypassing the Flash Controller. 250C Units Notes
Data Retention Endurance
100 10,000
- -
- -
years
cycles Program / erase cycles
Table 99. Watch-Dog Timer Electrical Characteristics and Timing VDD = 2.7 - 3.6V TA = -400C to 1050C Symbol FWDT Parameter WDT Oscillator Frequency Minimum Typical 5 10 Maximum 20 Units kHz Conditions
Table 100. Analog-to-Digital Converter Electrical Characteristics and Timing VDD = 2.7 - 3.6V TA = -400C to 1050C Symbol Parameter Resolution Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DC Offset Error
1
Minimum Typical - -1.0 -3.0 -35 10 - - -
Maximum - 1.0 3.0 35
Units bits LSB LSB mV
Conditions External VREF = 3.0V; RS <= 3.0k External VREF = 3.0V; RS <= 3.0k External VREF = 3.0V; RS <= 3.0k
Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
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Table 100. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued) VDD = 2.7 - 3.6V TA = -400C to 1050C Symbol VREF Parameter Internal Reference Voltage Single-Shot Conversion Time Continuous Conversion Time Sampling Rate Signal Input Bandwidth RS Zin Analog Source Impedance Input Impedance - - Minimum Typical 1.8 - - 2.0 5129 256 System Clock / 256 - - 150 3.5 101 Maximum 2.55 - - Units V cycles System clock cycles cycles System clock cycles Hz kHz k k 20MHz system clock. Input impedance increases with lower system clock frequency. AVDD <= VDD. When using an external reference voltage, decoupling capacitance should be placed from VREF to AVSS. Conditions
VREF
External Reference Voltage
AVDD
V
IREF
Current draw into VREF pin when driving with external source.
25.0
40.0
A
1
Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
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General Purpose I/O Port Input Data Sample Timing
Figure 40 illustrates timing of the GPIO Port input sampling. The input value on a GPIO Port pin is sampled on the rising edge of the system clock. The Port value is then available to the eZ8 CPU on the second rising clock edge following the change of the Port value.
TCLK
System Clock Port Value Changes to 0 Port Pin Input Value
Port Input Data Register Latch
0 Value May Be Read From Port Input Data Register
Figure 40. Port Input Sample Timing Table 101. GPIO Port Input Timing Delay (ns) Parameter TS_PORT TH_PORT TSMR Abbreviation Port Input Transition to XIN Rise Setup Time (Not pictured) XIN Rise to Port Input Transition Hold Time (Not pictured) GPIO Port Pin Pulse Width to Insure STOP Mode Recovery (for GPIO Port Pins enabled as SMR sources) Min 5 5 1s Max - -
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General Purpose I/O Port Output Timing
Figure 41 and Table 102 provide timing information for GPIO Port pins.
TCLK
XIN T1 Port Output T2
Figure 41. GPIO Port Output Timing Table 102. GPIO Port Output Timing Delay (ns) Parameter Abbreviation Min Max
GPIO Port pins T1 T2 XIN Rise to Port Output Valid Delay XIN Rise to Port Output Hold Time - 2 15 -
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On-Chip Debugger Timing
Figure 42 and Table 103 provide timing information for the DBG pin. The DBG pin timing specifications assume a 4ns maximum rise and fall time.
TCLK
XIN T1 DBG (Output) T2
Output Data
T3 DBG (Input)
T4
Input Data
Figure 42. On-Chip Debugger Timing Table 103. On-Chip Debugger Timing Delay (ns) Parameter DBG T1 T2 T3 T4 XIN Rise to DBG Valid Delay XIN Rise to DBG Output Hold Time DBG to XIN Rise Input Setup Time DBG to XIN Rise Input Hold Time - 2 10 5 15 - - - Abbreviation Min Max
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SPI MASTER Mode Timing
Figure 43 and Table 104 provide timing information for SPI MASTER mode pins. Timing is shown with SCK rising edge used to source MOSI output data, SCK falling edge used to sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK T1 MOSI (Output) T2
Output Data
T3
MISO (Input)
Input Data
Figure 43. SPI MASTER Mode Timing Table 104. SPI MASTER Mode Timing Delay (ns) Parameter Abbreviation Min Max
SPI MASTER T1 T2 T3 SCK Rise to MOSI output Valid Delay MISO input to SCK (receive edge) Setup Time MISO input to SCK (receive edge) Hold Time -5 20 0 +5
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SPI SLAVE Mode Timing
Figure 44 and Table 105 provide timing information for the SPI SLAVE mode pins. Timing is shown with SCK rising edge used to source MISO output data, SCK falling edge used to sample MOSI input data.
SCK T1 MISO (Output) T2
Output Data
T3
MOSI (Input) T4 SS (Input)
Input Data
Figure 44. SPI SLAVE Mode Timing Table 105. SPI SLAVE Mode Timing Delay (ns) Parameter SPI SLAVE T1 SCK (transmit edge) to MISO output Valid Delay 2 * Xin period 0 3 * Xin period 1 * Xin period 3 * Xin period + 20 nsec Abbreviation Min Max
T2 T3 T4
MOSI input to SCK (receive edge) Setup Time MOSI input to SCK (receive edge) Hold Time SS input assertion to SCK setup
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I2C Timing
Figure 45 and Table 106 provide timing information for I2C pins.
SCL (Output) T1 SDA (Output) T2 Input Data T3
Output Data
SDA (Input)
Figure 45. I2C Timing Table 106. I2C Timing Delay (ns) Parameter IC T1 T2 T3 SCL Fall to SDA output delay SDA Input to SCL rising edge Setup Time SDA Input to SCL falling edge Hold Time 0 0 SCL period/4
2
Abbreviation
Minimum
Maximum
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UART Timing
Figure 46 and Table 107 provide timing information for UART pins for the case where CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit data register has been loaded with data prior to CTS assertion.
CTS (Input)
T3
DE (Output) T1
TXD (Output)
bit7
parity
stop T2
start
bit0
bit
end of stop bit(s)
Figure 46. UART Timing with CTS Table 107. UART Timing with CTS Delay (ns) Parameter UART T1 T2 T3 CTS Fall to DE output delay DE assertion to TXD falling edge (start bit) delay End of Stop Bit(s) to DE deassertion delay 2 * XIN period 2 * XIN period + 1 bit time +/- 5 +/- 5 Abbreviation Minimum Maximum
Figure 47 and Table 108 provide timing information for UART pins for the case where CTS is not used for flow control. DE asserts after the transmit data register has been written. DE remains asserted for multiple characters as long as the transmit data register is written with the next character before the current character has completed.
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T2 DE (Output)
TXD (Output) T1
start
bit0
bit1
bit7
parity
stop
end of stop bit(s)
Figure 47. UART Timing without CTS Table 108. UART Timing without CTS Delay (ns) Parameter UART T1 T2 DE assertion to TXD falling edge (start bit) delay End of Stop Bit(s) to DE deassertion delay (Tx data register is empty) 1 * XIN period +/- 5 1 bit time Abbreviation Minimum Maximum
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eZ8 CPU Instruction Set
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program without having to be concerned with actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called statements. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label identifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine language program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example. Assembly Language Source Program Example
JP START START:
; Everything after the semicolon is a comment. ; A label called "START". The first instruction (JP START) in this ; example causes program execution to jump to the point within the ; program where the START label occurs. ; A Load (LD) instruction with two operands. The first operand, ; Working Register R4, is the destination. The second operand, ; Working Register R7, is the source. The contents of R7 is ; written into R4. ; Another Load (LD) instruction with two operands. ; The first operand, Extended Mode Register Address 234H, ; identifies the destination. The second operand, Immediate Data
LD R4, R7
LD 234H, #%01
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; value 01H, is the source. The value 01H is written into the ; Register at address 234H.
Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as `destination, source'. After assembly, the object code usually has the operands in the order 'source, destination', but ordering is opcode-dependent. The following instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. Example 1: If the contents of Registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is:
Table 109. Assembly Language Syntax Example 1 Assembly Language Code ADD Object Code 04 43H 08 08H 43 (ADD dst, src) (OPC src, dst)
Example 2: In general, when an instruction format requires an 8-bit register address, that address can specify any register location in the range 0 - 255 or, using Escaped Mode Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H, the assembly syntax and resulting object code is:
Table 110. Assembly Language Syntax Example 2 Assembly Language Code ADD Object Code 04 43H, E8 R8 43 (ADD dst, src) (OPC src, dst)
See the device-specific Product Specification to determine the exact register file range available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition codes, status flags, and address modes are represented by a notational shorthand that is described in Table 111
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.
Table 111. Notational Shorthand Notation Description b cc DA ER IM Ir IR Irr IRR p r R RA Bit Condition Code Direct Address Extended Addressing Register Immediate Data Indirect Working Register Indirect Register Indirect Working Register Pair Indirect Register Pair Polarity Working Register Register Relative Address Operand Range b -- Addrs Reg #Data @Rn @Reg @RRp @Reg p Rn Reg X b represents a value from 0 to 7 (000B to 111B). See Condition Codes overview in the eZ8 CPU User Manual. Addrs. represents a number in the range of 0000H to FFFFH Reg. represents a number in the range of 000H to FFFH Data is a number between 00H to FFH n = 0 -15 Reg. represents a number in the range of 00H to FFH p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range 00H to FEH Polarity is a single bit binary value of either 0B or 1B. n = 0 - 15 Reg. represents a number in the range of 00H to FFH X represents an index in the range of +127 to -128 which is an offset relative to the address of the next instruction p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range of 00H to FEH Vector represents a number in the range of 00H to FFH The register or register pair to be indexed is offset by the signed Index value (#Index) in a +127 to -128 range.
rr RR Vector X
Working Register Pair Register Pair Vector Address Indexed
RRp Reg Vector #Index
Table 112 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections.
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Table 112. Additional Symbols Symbol dst src @ SP PC FLAGS RP # B % H Definition Destination Operand Source Operand Indirect Address Prefix Stack Pointer Program Counter Flags Register Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix
Assignment of a value is indicated by an arrow. For example, dst dst + src indicates the source data is added to the destination data and the result is stored in the destination location.
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Condition Codes
The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc) instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which forms Bits 7:4 of the conditional jump instructions. The condition codes are summarized in Table 113. Some binary condition codes can be created using more than one assembly code mnemonic. The result of the flag test operation decides if the conditional jump is executed.
Table 113. Condition Codes Assembly Mnemonic Definition F LT LE ULE OV Ml Z EQ C ULT Always False Less Than Less Than or Equal Unsigned Less Than or Equal Overflow Minus Zero Equal Carry Unsigned Less Than
Binary 0000 0001 0010 0011 0100 0101 0110 0110 0111 0111 1000 1001 1010 1011 1100 1101 1110 1110 1111 1111
Hex 0 1 2 3 4 5 6 6 7 7 8 9 A B C D E E F F
Flag Test Operation - (S XOR V) = 1 (Z OR (S XOR V)) = 1 (C OR Z) = 1 V=1 S=1 Z=1 Z=1 C=1 C=1 - (S XOR V) = 0 (Z OR (S XOR V)) = 0 (C = 0 AND Z = 0) = 1 V=0 S=0 Z=0 Z=0 C=0
T (or blank) Always True GE GT UGT NOV PL NZ NE NC UGE Greater Than or Equal Greater Than Unsigned Greater Than No Overflow Plus Non-Zero Not Equal No Carry
Unsigned Greater Than or Equal C = 0
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eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
* * * * * * * *
Arithmetic Bit Manipulation Block Transfer CPU Control Load Logical Program Control Rotate and Shift
Tables 114 through 121 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the source operand is identified as 'src', the destination operand is 'dst' and a condition code is 'cc'.
Table 114. Arithmetic Instructions Mnemonic ADC ADCX ADD ADDX CP CPC CPCX CPX DA DEC DECW INC INCW MULT Operands dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst dst dst dst dst dst Instruction Add with Carry Add with Carry using Extended Addressing Add Add using Extended Addressing Compare Compare with Carry Compare with Carry using Extended Addressing Compare using Extended Addressing Decimal Adjust Decrement Decrement Word Increment Increment Word Multiply
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Table 114. Arithmetic Instructions (Continued) Mnemonic SBC SBCX SUB SUBX Operands dst, src dst, src dst, src dst, src Instruction Subtract with Carry Subtract with Carry using Extended Addressing Subtract Subtract using Extended Addressing
Table 115. Bit Manipulation Instructions Mnemonic BCLR BIT BSET BSWAP CCF RCF SCF TCM TCMX TM TMX Operands bit, dst p, bit, dst bit, dst dst -- -- -- dst, src dst, src dst, src dst, src Instruction Bit Clear Bit Set or Clear Bit Set Bit Swap Complement Carry Flag Reset Carry Flag Set Carry Flag Test Complement Under Mask Test Complement Under Mask using Extended Addressing Test Under Mask Test Under Mask using Extended Addressing
Table 116. Block Transfer Instructions Mnemonic LDCI LDEI Operands dst, src dst, src Instruction Load Constant to/from Program Memory and Auto-Increment Addresses Load External Data to/from Data Memory and Auto-Increment Addresses
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Table 117. CPU Control Instructions Mnemonic CCF DI EI HALT NOP RCF SCF SRP STOP WDT Operands -- -- -- -- -- -- -- src -- -- Instruction Complement Carry Flag Disable Interrupts Enable Interrupts HALT Mode No Operation Reset Carry Flag Set Carry Flag Set Register Pointer STOP Mode Watch-Dog Timer Refresh
Table 118. Load Instructions Mnemonic CLR LD LDC LDCI LDE LDEI LDX LEA POP POPX PUSH PUSHX Operands Instruction dst dst, src dst, src dst, src dst, src dst, src dst, src Clear Load Load Constant to/from Program Memory Load Constant to/from Program Memory and Auto-Increment Addresses Load External Data to/from Data Memory Load External Data to/from Data Memory and Auto-Increment Addresses Load using Extended Addressing
dst, X(src) Load Effective Address dst dst src src Pop Pop using Extended Addressing Push Push using Extended Addressing
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Table 119. Logical Instructions Mnemonic Operands Instruction AND ANDX COM OR ORX XOR XORX dst, src dst, src dst dst, src dst, src dst, src dst, src Logical AND Logical AND using Extended Addressing Complement Logical OR Logical OR using Extended Addressing Logical Exclusive OR Logical Exclusive OR using Extended Addressing
Table 120. Program Control Instructions Mnemonic BRK BTJ BTJNZ BTJZ CALL DJNZ IRET JP JP cc JR JR cc RET TRAP Operands -- Instruction On-Chip Debugger Break
p, bit, src, DA Bit Test and Jump bit, src, DA bit, src, DA dst dst, src, RA -- dst dst DA DA -- vector Bit Test and Jump if Non-Zero Bit Test and Jump if Zero Call Procedure Decrement and Jump Non-Zero Interrupt Return Jump Jump Conditional Jump Relative Jump Relative Conditional Return Software Trap
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Table 121. Rotate and Shift Instructions Mnemonic BSWAP RL RLC RR RRC SRA SRL SWAP Operands dst dst dst dst dst dst dst dst Instruction Bit Swap Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Shift Right Arithmetic Shift Right Logical Swap Nibbles
eZ8 CPU Instruction Summary
Table 122 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.
.
Table 122. eZ8 CPU Instruction Summary Assembly Mnemonic ADC dst, src Address Mode Symbolic Operation dst dst + src + C dst r r R R R IR ADCX dst, src dst dst + src + C ER ER Flags Notation: src r Ir R IR IM IM ER IM Opcode(s) (Hex) C 12 13 14 15 16 17 18 19 0 = Reset to 0 1 = Set to 1 * * * * 0 * * Flags Z * S * Fetch Instr. V D H Cycles Cycles * 0 * 2 2 3 3 3 3 4 4 3 4 3 4 3 4 3 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic ADD dst, src Address Mode Symbolic Operation dst dst + src dst r r R R R IR ADDX dst, src dst dst + src dst dst AND src ER ER AND dst, src r r R R R IR ANDX dst, src dst dst AND src dst[bit] 0 dst[bit] p Debugger Break dst[bit] 1 dst[7:0] dst[0:7] r R r Ir r Ir ER ER BCLR bit, dst BIT p, bit, dst BRK BSET bit, dst BSWAP dst r r src r Ir R IR IM IM ER IM r Ir R IR IM IM ER IM Opcode(s) (Hex) C 02 03 04 05 06 07 08 09 52 53 54 55 56 57 58 59 E2 E2 00 E2 D5 F6 F7 F6 F7 0 = Reset to 0 1 = Set to 1 X * * * * * * * * 0 0 0 0 * * 0 * * 0 * * * * 0 * * Flags Z * S * Fetch Instr. V D H Cycles Cycles * 0 * 2 2 3 3 3 3 4 4 2 2 3 3 3 3 4 4 2 2 1 2 2 3 3 3 3 3 4 3 4 3 4 3 3 3 4 3 4 3 4 3 3 2 2 1 2 2 3 4 3 4
BTJ p, bit, src, dst if src[bit] = p PC PC + X BTJNZ bit, src, dst if src[bit] = 1 PC PC + X Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic BTJZ bit, src, dst Address Mode Symbolic Operation if src[bit] = 0 PC PC + X SP SP -2 @SP PC PC dst C ~C dst 00H dst ~dst R IR COM dst R IR CP dst, src dst - src r r R R R IR CPC dst, src dst - src - C r r R R R IR CPCX dst, src dst - src - C ER ER CPX dst, src dst - src ER ER Flags Notation: r Ir R IR IM IM r Ir R IR IM IM ER IM ER IM IRR DA dst src r Ir Opcode(s) (Hex) C F6 F7 D4 D6 EF B0 B1 60 61 A2 A3 A4 A5 A6 A7 1F A2 1F A3 1F A4 1F A5 1F A6 1F A7 1F A8 1F A9 A8 A9 0 = Reset to 0 1 = Set to 1 * * * * * * * * * * * * * * * * * * 0 * Flags Z S Fetch Instr. V D H Cycles Cycles 3 3 2 3 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 5 5 4 4 3 4 6 3 2 2 3 2 3 3 4 3 4 3 4 3 4 3 4 3 4 3 3 3 3
CALL dst
CCF CLR dst
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic DA dst Address Mode Symbolic Operation dst DA(dst) dst dst - 1 dst dst - 1 IRQCTL[7] 0 dst dst - 1 if dst 0 PC PC + X IRQCTL[7] 1 HALT Mode dst dst + 1 R IR r INCW dst dst dst + 1 FLAGS @SP SP SP + 1 PC @SP SP SP + 2 IRQCTL[7] 1 PC dst DA IRR JP cc, dst JR dst JR cc, dst Flags Notation: if cc is true PC dst PC PC + X if cc is true PC PC + X DA DA DA RR IRR IRET r dst R IR DEC dst R IR DECW dst RR IRR DI DJNZ dst, RA src Opcode(s) (Hex) C 40 41 30 31 80 81 8F 0A-FA * * * * * * * Flags Z * S * Fetch Instr. V D H Cycles Cycles 2 2 2 2 2 2 1 2 2 3 2 3 5 6 2 3
X
EI HALT INC dst
9F 7F 20 21 0E-FE A0 A1 BF
-
*
*
*
-
-
1 1 2 2 1
2 2 2 3 2 5 6 5
-
*
*
*
-
-
2 2
*
*
*
*
*
*
1
JP dst
8D C4 0D-FD 8B 0B-FB
-
-
-
-
-
-
3 2
2 3 2 2 2
-
-
-
-
-
-
3 2 2
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic LD dst, rc Address Mode Symbolic Operation dst src dst r r X(r) r R R R IR Ir IR LDC dst, src dst src r Ir Irr LDCI dst, src dst src rr+1 rr rr + 1 dst src dst src rr+1 rr rr + 1 Ir Irr r Irr LDEI dst, src Ir Irr src IM X(r) r Ir R IR IM IM r R Irr Irr r Irr Ir Irr r Irr Ir Opcode(s) (Hex) C 0C-FC C7 D7 E3 E4 E5 E6 E7 F3 F5 C2 C5 D2 C3 D3 82 92 83 93 0 = Reset to 0 1 = Set to 1 Flags Z S Fetch Instr. V D H Cycles Cycles 2 3 3 2 3 3 3 3 2 3 2 2 2 2 2 2 2 2 2 2 3 4 3 2 4 2 3 3 3 5 9 5 9 9 5 5 9 9
LDE dst, src
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic LDX dst, src Address Mode Symbolic Operation dst src dst r Ir R IR r X(rr) ER ER IRR IRR ER ER LEA dst, X(src) dst src + X dst[15:0] dst[15:8] * dst[7:0] No operation dst dst OR src r r R R R IR ORX dst, src dst dst OR src ER ER Flags Notation: r Ir R IR IM IM ER IM r rr MULT dst NOP OR dst, src RR src ER ER IRR IRR X(rr) r r Ir R IR ER IM X(r) X(rr) Opcode(s) (Hex) C 84 85 86 87 88 89 94 95 96 97 E8 E9 98 99 F4 0F 42 43 44 45 46 47 48 49 0 = Reset to 0 1 = Set to 1 * * 0 * * 0 Flags Z S Fetch Instr. V D H Cycles Cycles 3 3 3 3 3 3 3 3 3 3 4 4 3 3 2 1 2 2 3 3 3 3 4 4 2 3 4 5 4 4 2 3 4 5 2 2 3 5 8 2 3 4 3 4 3 4 3 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic POP dst Address Mode Symbolic Operation dst @SP SP SP + 1 dst @SP SP SP + 1 SP SP - 1 @SP src SP SP - 1 @SP src C0 PC @SP SP SP + 2 R
C D7 D6 D5 D4 D3 D2 D1 D0 dst
dst R IR ER R IR ER
src
Opcode(s) (Hex) C 50 51 D8 70 71 C8 CF AF 90 91 0 * -
Flags Z S -
Fetch Instr. V D H Cycles Cycles 2 2 2 3 2 2 3 2 2 4 2 3
POPX dst PUSH src
-
-
-
-
-
3 2 2
PUSHX src RCF RET RL dst
*
*
*
-
-
3 1 1 2 2
IR
RLC dst
C D7 D6 D5 D4 D3 D2 D1 D0 dst
R IR R
D7 D6 D5 D4 D3 D2 D1 D0 dst C
10 11 E0 E1
*
*
*
*
-
-
2 2
2 3 2 3
RR dst
*
*
*
*
-
-
2 2
IR
RRC dst
D7 D6 D5 D4 D3 D2 D1 D0 dst C
R IR
C0 C1
*
*
*
*
-
-
2 2
2 3
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic SBC dst, src Address Mode Symbolic Operation dst dst - src - C dst r r R R R IR SBCX dst, src dst dst - src - C C1 R
D7 D6 D5 D4 D3 D2 D1 D0 dst C
src r Ir R IR IM IM ER IM
Opcode(s) (Hex) C 32 33 34 35 36 37 38 39 DF D0 D1 1 * * *
Flags Z * S *
Fetch Instr. V D H Cycles Cycles * 1 * 2 2 3 3 3 3 3 4 3 4 3 4 3 3 2 2 3
ER ER
*
*
*
1
*
4 4
SCF SRA dst
*
*
0
-
-
1 2 2
IR
SRL dst
0
D7 D6 D5 D4 D3 D2 D1 D0 dst
C
R IR
1F C0 1F C1 IM 01 6F
*
*
0
*
-
-
3 3
2 3 2 2 3 4 3 4 3 4 3 3 2 3
SRP src STOP SUB dst, src
RP src Stop Mode dst dst - src r r R R R IR dst dst - src dst[7:4] dst[3:0]
*
*
*
*
1
*
2 1 2 2 3 3 3 3
r Ir R IR IM IM ER IM
22 23 24 25 26 27 28 29 F0 F1
SUBX dst, src
ER ER
*
*
*
*
1
*
4 4
SWAP dst
R IR
X
*
*
X
-
-
2 2
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic TCM dst, src Address Mode Symbolic Operation (NOT dst) AND src dst r r R R R IR TCMX dst, src (NOT dst) AND src ER ER TM dst, src dst AND src r r R R R IR TMX dst, src dst AND src SP SP - 2 @SP PC SP SP - 1 @SP FLAGS PC @Vector ER ER TRAP Vector src r Ir R IR IM IM ER IM r Ir R IR IM IM ER IM Vector Opcode(s) (Hex) C 62 63 64 65 66 67 68 69 72 73 74 75 76 77 78 79 F2 * * 0 * * 0 * * 0 Flags Z * S * Fetch Instr. V D H Cycles Cycles 0 2 2 3 3 3 3 4 4 2 2 3 3 3 3 4 4 2 3 4 3 4 3 4 3 3 3 4 3 4 3 4 3 3 6
WDT Flags Notation:
5F * = Value is a function of the result of the operation. - = Unaffected X = Undefined
-
-
-
-
-
-
1
2
0 = Reset to 0 1 = Set to 1
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eZ8 CPU Instruction Set
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Table 122. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic XOR dst, src Address Mode Symbolic Operation dst dst XOR src dst r r R R R IR XORX dst, src dst dst XOR src ER ER Flags Notation: src r Ir R IR IM IM ER IM Opcode(s) (Hex) C B2 B3 B4 B5 B6 B7 B8 B9 0 = Reset to 0 1 = Set to 1 * * 0 Flags Z * S * Fetch Instr. V D H Cycles Cycles 0 2 2 3 3 3 3 4 4 3 4 3 4 3 4 3 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Flags Register
The Flags Register contains the status information regarding the most recent arithmetic, logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z and S) can be tested with conditional jump instructions. Two flags (H and D) cannot be tested and are used for Binary-Coded Decimal (BCD) arithmetic. The two remaining bits, User Flags (F1 and F2), are available as general-purpose status bits. User Flags are unaffected by arithmetic operations and must be set or cleared by instructions. The User Flags cannot be used with conditional Jumps. They are undefined at initial power-up and are unaffected by Reset. Figure 48 illustrates the flags and their bit positions in the Flags Register.
Bit 7 C Z S V D H Bit 0 F2 F1 Flags Register User Flags Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 48. Flags Register
Interrupts, the Software Trap (TRAP) instruction, and Illegal Instruction Traps all write the value of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruction restores the value saved on the stack into the Flags Register.
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Opcode Maps
Figures 50 and 51 provide information on each of the eZ8 CPU instructions. A description of the opcode map data and the abbreviations are provided in Figure 49 and Table 123.
Opcode Lower Nibble Fetch Cycles Instruction Cycles
4
3.3 Opcode Upper Nibble
A
CP R2,R1
First Operand After Assembly
Second Operand After Assembly
Figure 49. Opcode Map Cell Description
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Table 123. Opcode Map Abbreviations Abbreviation b cc X DA ER IM Ir IR Irr Description Bit position Condition code Abbreviation IRR p Description Indirect Register Pair Polarity (0 or 1) 4-bit Working Register 8-bit register
8-bit signed index or displacement r Destination address Extended Addressing register Immediate data value Indirect Working Register Indirect register Indirect Working Register Pair R
r1, R1, Ir1, Irr1, IR1, rr1, Destination address RR1, IRR1, ER1 r2, R2, Ir2, Irr2, IR2, rr2, Source address RR2, IRR2, ER2 RA rr RR Relative Working Register Pair Register Pair
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Opcode Maps
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0
1.2
1
2.2
2
2.3
3
2.4
4
3.3
5
3.4
6
3.3
Lower Nibble (Hex) 7 8 9
3.4 4.3 4.3
A
2.3 r1,X
B
2.2
C
2.2
D
3.2
E
1.2
F
1.2
0
BRK
2.2
SRP
IM 2.3
ADD
r1,r2 2.3
ADD
r1,Ir2 2.4
ADD
R2,R1 3.3
ADD
IR2,R1 3.4
ADD
R1,IM 3.3
ADD
3.4
ADDX ADDX DJNZ
4.3 4.3
JR
cc,X
LD
r1,IM
JP
cc,DA
INC
r1
NOP
See 2nd Opcode Map
IR1,IM ER2,ER1 IM,ER1
1
RLC
R1 2.2
RLC
IR1 2.3
ADC
r1,r2 2.3
ADC
r1,Ir2 2.4
ADC
R2,R1 3.3
ADC
IR2,R1 3.4
ADC
R1,IM 3.3
ADC
3.4
ADCX ADCX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
2
INC
R1 2.2
INC
IR1 2.3
SUB
r1,r2 2.3
SUB
r1,Ir2 2.4
SUB
R2,R1 3.3
SUB
IR2,R1 3.4
SUB
R1,IM 3.3
SUB
3.4
SUBX SUBX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
3
DEC
R1 2.2
DEC
IR1 2.3
SBC
r1,r2 2.3
SBC
r1,Ir2 2.4
SBC
R2,R1 3.3
SBC
IR2,R1 3.4
SBC
R1,IM 3.3
SBC
3.4
SBCX SBCX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
4
DA
R1 2.2
DA
IR1 2.3
OR
r1,r2 2.3
OR
r1,Ir2 2.4
OR
R2,R1 3.3
OR
IR2,R1 3.4
OR
R1,IM 3.3
OR
3.4
ORX
4.3
ORX
4.3 1.2
IR1,IM ER2,ER1 IM,ER1
5
POP
R1 2.2
POP
IR1 2.3
AND
r1,r2 2.3
AND
r1,Ir2 2.4
AND
R2,R1 3.3
AND
IR2,R1 3.4
AND
R1,IM 3.3
AND
3.4
ANDX ANDX
4.3 4.3
WDT
1.2
IR1,IM ER2,ER1 IM,ER1
6 Upper Nibble (Hex)
COM
R1 2.2
COM
IR1 2.3 IR2 2.6 IRR1 2.3
TCM
r1,r2 2.3
TCM
r1,Ir2 2.4
TCM
R2,R1 3.3
TCM
IR2,R1 3.4
TCM
R1,IM 3.3
TCM
3.4
TCMX TCMX
4.3 4.3
STOP
1.2
IR1,IM ER2,ER1 IM,ER1
7
PUSH PUSH
R2 2.5
TM
r1,r2 2.5
TM
r1,Ir2 2.9
TM
R2,R1 3.2
TM
IR2,R1 3.3
TM
R1,IM 3.4
TM
3.5
TMX
3.4
TMX
3.4
HALT
1.2
IR1,IM ER2,ER1 IM,ER1
8
DECW DECW
RR1 2.2
LDE
r1,Irr2 2.5
LDEI
Ir1,Irr2 2.9
LDX
r1,ER2 3.2
LDX
3.3
LDX
3.4
LDX
3.5
LDX
3.3
LDX
rr1,r2,X 3.5
DI
1.2
Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X
9
RL
R1 2.5
RL
IR1 2.6 IRR1 2.3
LDE
r2,Irr1 2.3
LDEI
Ir2,Irr1 2.4
LDX
r2,ER1 3.3
LDX
3.4
LDX
3.3
LDX
3.4
LEA
4.3
LEA
rr1,rr2,X 4.3
EI
1.4
Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X
A
INCW INCW
RR1 2.2
CP
r1,r2 2.3
CP
r1,Ir2 2.4
CP
R2,R1 3.3
CP
IR2,R1 3.4
CP
R1,IM 3.3
CP
3.4
CPX
4.3
CPX
4.3
RET
1.5
IR1,IM ER2,ER1 IM,ER1
B
CLR
R1 2.2
CLR
IR1 2.3
XOR
r1,r2 2.5
XOR
r1,Ir2 2.9
XOR
R2,R1 2.3
XOR
IR2,R1 2.9
XOR
R1,IM
XOR
3.4
XORX XORX
3.2
IRET
1.2
IR1,IM ER2,ER1 IM,ER1
C
RRC
R1 2.2
RRC
IR1 2.3
LDC
r1,Irr2 2.5
LDCI
Ir1,Irr2 2.9
JP
IRR1 2.6 IRR1 3.2
LDC
Ir1,Irr2 2.2 R1 3.3 3.3 DA 3.2
LD
r1,r2,X 3.4
PUSHX
ER2 3.2
RCF
1.2
D
SRA
R1 2.2
SRA
IR1 2.3
LDC
r2,Irr1 2.2
LDCI
Ir2,Irr1 2.3
CALL BSWAP CALL
LD
r2,r1,X 3.3
POPX
ER1 4.2 4.2
SCF
1.2
E
RR
R1 2.2
RR
IR1 2.3 IR1
BIT
p,b,r1 2.6 Vector
LD
r1,Ir2 2.3
LD
R2,R1 2.8
LD
IR2,R1 3.3
LD
R1,IM 3.3
LD
3.4
LDX
LDX
CCF
IR1,IM ER2,ER1 IM,ER1
F
SWAP SWAP TRAP
R1
LD
Ir1,r2
MULT
RR1
LD
R2,IR1
BTJ
BTJ
p,b,r1,X p,b,Ir1,X
Figure 50. First Opcode Map
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Opcode Maps
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
211
0 0
1
2
3
4
5
6
Lower Nibble (Hex) 7 8 9
A
B
C
D
E
F
1
2
3
4
5
6 Upper Nibble (Hex)
7
8
9
3.3 3.4 4.3 4.4 4.3 4.4 5.3 5.3
A
CPC
r1,r2
CPC
r1,Ir2
CPC
R2,R1
CPC
IR2,R1
CPC
R1,IM
CPC
CPCX CPCX
IR1,IM ER2,ER1 IM,ER1
B
3.2 3.3
C
SRL
R1
SRL
IR1
D
E
F
Figure 51. Second Opcode Map after 1FH
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Preliminary
Opcode Maps
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
212
Packaging
Figure 52 illustrates the 20-pin SSOP package available for the Z8F0411, Z8F0421, Z8F0811, and Z8F0821 devices.
Figure 52. 20-Pin Small Shrink Outline Package (SSOP)
PS019707-1003
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Packaging
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
213
Figure 53 illustrates the 20-pin PDIP package available for the Z8F0411, Z8F0421, Z8F0811, and Z8F0821 devices.
Figure 53. 20-Pin Plastic Dual-Inline Package (PDIP)
PS019707-1003
Preliminary
Packaging
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
214
Figure 54 illustrates the 28-pin SOIC package available for the Z8F0412, Z8F0422, Z8F0812, and Z8F0822 devices.
Figure 54. 28-Pin Small Outline Integrated Circuit Package (SOIC)
PS019707-1003
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Packaging
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
215
Figure 55 illustrates the 28-pin PDIP package available for the Z8F0412, Z8F0422, Z8F0812, and Z8F0822 devices.
Figure 55. 28-Pin Plastic Dual-Inline Package (PDIP)
PS019707-1003
Preliminary
Packaging
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
216
Ordering Information
Table 124. Ordering Information Flash RAM Max. Speed KB (Bytes) KB (Bytes) (MHz) Temp (0C) Voltage (V) Part Z8 Encore!(R) Encore!(R) Encore!(R) Z8 Encore!(R) Z8 Z8 Encore!(R) Z8 Package Part Number
with 8KB Flash and 10-Bit Analog-to-Digital Converter (Standard Temperature) 8 (8192) 8 (8192) 8 (8192) 8 (8192) 1 (1024) 1 (1024) 1 (1024) 1 (1024) 20 20 20 20 0 to +70 0 to +70 0 to +70 0 to +70 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 SSOP-20 PDIP-20 SOIC-28 PDIP-28 Z8F0821HH020SC Z8F0821PH020SC Z8F0822SJ020SC Z8F0822PJ020SC
Z8 Encore!(R) with 8KB Flash and 10-Bit Analog-to-Digital Converter (Extended Temperature) Z8 Encore!(R) Z8 Encore!(R) Z8 Encore!(R)
(R)
8 (8192) 8 (8192) 8 (8192) 8 (8192)
1 (1024) 1 (1024) 1 (1024) 1 (1024)
20 20 20 20
-40 to +105 -40 to +105 -40 to +105 -40 to +105
2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6
SSOP-20 PDIP-20 SOIC-28 PDIP-28
Z8F0821HH020EC Z8F0821PH020EC Z8F0822SJ020EC Z8F0822PJ020EC
Z8 Encore!(R) Z8 Encore!(R) Z8 Encore!
(R)
Z8 Encore! with 8KB Flash (Standard Temperature) 8 (8192) 8 (8192) 8 (8192) 8 (8192) 1 (1024) 1 (1024) 1 (1024) 1 (1024) 20 20 20 20 0 to +70 0 to +70 0 to +70 0 to +70 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 SSOP-20 PDIP-20 SOIC-28 PDIP-28 Z8F0811HH020SC Z8F0811PH020SC Z8F0812SJ020SC Z8F0812PJ020SC
Z8 Encore!(R) Z8 Encore!
(R)
Z8 Encore!(R) with 8KB Flash (Extended Temperature) Z8 Encore!(R) Z8 Encore!(R) Z8 Encore!
(R)
8 (8192) 8 (8192) 8 (8192) 8 (8192)
1 (1024) 1 (1024) 1 (1024) 1 (1024)
20 20 20 20
-40 to +105 -40 to +105 -40 to +105 -40 to +105
2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6
SSOP-20 PDIP-20 SOIC-28 PDIP-28
Z8F0811HH020EC Z8F0811PH020EC Z8F0812SJ020EC Z8F0812PJ020EC
Z8 Encore!(R)
PS019707-1003
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Ordering Information
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
217
Table 124. Ordering Information (Continued) Flash RAM Max. Speed KB (Bytes) KB (Bytes) (MHz) Temp (0C) Voltage (V)
Part Z8 Encore!(R) Z8 Encore!(R) Z8 Encore!(R) Encore!(R) Encore!(R) Encore!(R) Z8 Encore!(R) Z8 Z8 Encore!(R) Z8 Z8 Encore!(R) Z8
Package
Part Number
Z8 Encore!(R) with 4KB Flash and 10-Bit Analog-to-Digital Converter (Standard Temperature) 4 (4096) 4 (4096) 4 (4096) 4 (4096) 1 (1024) 1 (1024) 1 (1024) 1 (1024) 20 20 20 20 0 to +70 0 to +70 0 to +70 0 to +70 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 SSOP-20 PDIP-20 SOIC-28 PDIP-28 Z8F0421HH020SC Z8F0421PH020SC Z8F0422SJ020SC Z8F0422PJ020SC
with 4KB Flash and 10-Bit Analog-to-Digital Converter (Extended Temperature) 4 (4096) 4 (4096) 4 (4096) 4 (4096) 1 (1024) 1 (1024) 1 (1024) 1 (1024) 20 20 20 20 -40 to +105 -40 to +105 -40 to +105 -40 to +105 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 SSOP-20 PDIP-20 SOIC-28 PDIP-28 Z8F0421HH020EC Z8F0421PH020EC Z8F0422SJ020EC Z8F0422PJ020EC
Z8 Encore!(R) with 4KB Flash (Standard Temperature) Z8 Encore!(R) Z8 Encore!(R) Z8 Encore!
(R)
4 (4096) 4 (4096) 4 (4096) 4 (4096)
1 (1024) 1 (1024) 1 (1024) 1 (1024)
20 20 20 20
0 to +70 0 to +70 0 to +70 0 to +70
2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6
SSOP-20 PDIP-20 SOIC-28 PDIP-28
Z8F0411HH020SC Z8F0411PH020SC Z8F0412SJ020SC Z8F0412PJ020SC
Z8 Encore!(R)
(R)
Z8 Encore! with 4KB Flash (Extended Temperature) Z8 Encore!(R) Z8 Encore!
(R)
4 (4096) 4 (4096) 4 (4096) 4 (4096)
1 (1024) 1 (1024) 1 (1024) 1 (1024)
20 20 20 20
-40 to +105 -40 to +105 -40 to +105 -40 to +105
2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6
SSOP-20 PDIP-20 SOIC-28 PDIP-28
Z8F0411HH020EC Z8F0411PH020EC Z8F0412SJ020EC Z8F0412PK020EC
Z8 Encore!(R) Z8 Encore!
(R)
Z8 Encore!(R) Evaluation Kit Z8F082x Evaluation Kit Z8F08200100KIT
For valuable information about customer and technical support as well as hardware and software development tools, visit the ZiLOG web site at www.zilog.com. The latest released version of ZDS can be downloaded from this site.
PS019707-1003
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Ordering Information
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
218
Part Number Description
ZiLOG part numbers consist of a number of components, as indicated in the following examples:
ZiLOG Base Products Z8 F0821 HH 020 S C ZiLOG 8-bit microcontroller product Product Number Package Speed Temperature Environmental Flow
Packages
HH = 20-pin SSOP PH = 20-pin PDIP SJ = 28-pin SOIC PJ = 28-pin PDIP 020 = 20 MHz S = 0C to +70C E = -40C to +105C
Speed Temperature Environmental Flow
C = Plastic-Standard
For example, Part number Z8F0821HH020SC is an 8-bit microcontroller product in a 20pin SSOP package, operating with a maximum 20-MHz external clock frequency over a 0C to +70C temperature range and built using the Plastic-Standard environmental flow.
PS019707-1003
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Ordering Information
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
219
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues. ZiLOG, Inc. 532 Race Street San Jose, CA 95126 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.zilog.com
Document Information
Document Number Description
The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table:
PS 0197 07 1003 Product Specification Unique Document Number Revision Number Month and Year Published
Customer Feedback Form
The Z8 Encore!(R) Product Specification
If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions!
Customer Information
Name Company Address City/State/Zip Country Phone Fax E-Mail
PS019707-1003
Preliminary
Ordering Information
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
220
Product Information
Part #, Serial #, Board Fab #, or Rev. # Software Version Document Number Host Computer Description/Type
Return Information
ZiLOG 532 Race Street San Jose, CA 95126 Fax: (408) 558-8536
PS019707-1003
Preliminary
Ordering Information
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
221
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________
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Index
Symbols
# 191 % 191 @ 191
analog-to-digital converter (ADC) 133 AND 196 ANDX 196 arithmetic instructions 193 assembly language programming 188 assembly language syntax 189
B
B 191 b 190 baud rate generator, UART 91 BCLR 194 binary number suffix 191 BIT 194 bit 190 clear 194 manipulation instructions 194 set 194 set or clear 194 swap 194 test and jump 196 test and jump if non-zero 196 test and jump if zero 196 bit jump and test if non-zero 196 Bit Numbering xviii bit swap 197 Bits and Similar Registers, Notation for xvii block diagram 3 block transfer instructions 194 Braces xvii Brackets xvi BRK 196 BSET 194 BSWAP 194, 197 BTJ 196 BTJNZ 196 BTJZ 196
Numerics
10-bit ADC 4 40-lead plastic dual-inline package 214
A
About This Manual xvi absolute maximum ratings 171 AC characteristics 175 ADC 193 architecture 133 automatic power-down 134 block diagram 134 continuous conversion 135 control register 136 control register definitions 136 data high byte register 137 data low bits register 138 electrical characteristics and timing 178 operation 134 single-shot conversion 134 ADCCTL register 136 ADCDH register 137 ADCDL register 138 ADCX 193 ADD 193 add - extended addressing 193 add with carry 193 add with carry - extended addressing 193 additional symbols 191 address space 13 ADDX 193 All Uppercase Letters, Use of xviii analog signals 10
C
CALL procedure 196 capture mode 74 capture/compare mode 74
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
223
cc 190 CCF 195 characteristics, electrical 171 clear 195 clock phase (SPI) 110 CLR 195 COM 196 compare 74 compare - extended addressing 193 compare mode 74 compare with carry 193 compare with carry - extended addressing 193 complement 196 complement carry flag 194, 195 condition code 190 continuous conversion (ADC) 135 continuous mode 73 control register definition, UART 92 control register, I2C 129 counter modes 73 Courier Typeface xvi CP 193 CPC 193 CPCX 193 CPU and peripheral overview 4 CPU control instructions 195 CPX 193 customer feedback form 219 customer information 219
DI 195 direct address 190 disable interrupts 195 DJNZ 196 DMA controller 5 document number description 219 dst 191
E
EI 195 electrical characteristics 171 ADC 178 flash memory and timing 177 GPIO input data sample timing 180 watch-dog timer 178 enable interrupt 195 ER 190 extended addressing register 190 external pin reset 33 eZ8 CPU features 4 eZ8 CPU instruction classes 193 eZ8 CPU instruction notation 189 eZ8 CPU instruction set 188 eZ8 CPU instruction summary 197
F
FCTL register 145 features, Z8 Encore! 1 first opcode map 210 FLAGS 191 flags register 191 flash controller 4 option bit address space 150 option bit configuration - reset 150 program memory address 0000H 151 program memory address 0001H 152 flash memory 139 arrrangement 140 byte programming 143 code protection 142
D
DA 190, 193 data register, I2C 127 DC characteristics 173 debugger, on-chip 153 DEC 193 decimal adjust 193 decrement 193 decrement and jump non-zero 196 decrement word 193 DECW 193 destination operand 191 device, port availability 37
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
224
configurations 139 control register definitions 145 controller bypass 144 electrical characteristics and timing 177 flash control register 145 flash status register 146 frequency high and low byte registers 149 mass erase 144 operation 141 operation timing 141 page erase 144 page select register 147 FPS register 147 FSTAT register 146
hexadecimal number prefix/suffix 191 Hexadecimal Values xvi
I
I2C 4 10-bit address read transaction 126 10-bit address transaction 124 10-bit addressed slave data transfer format 124 10-bit receive data format 126 7-bit address transaction 123 7-bit address, reading a transaction 125 7-bit addressed slave data transfer format 123 7-bit receive data transfer format 125 baud high and low byte registers 130, 132 C status register 128 control register definitions 127 controller 121 controller signals 9 interrupts 122 operation 121 SDA and SCL signals 121 stop and start conditions 122 I2CBRH register 131, 132 I2CBRL register 131 I2CCTL register 129 I2CDATA register 128 I2CSTAT register 128 IM 190 immediate data 190 immediate operand prefix 191 INC 193 increment 193 increment word 193 INCW 193 indexed 190 indirect address prefix 191 indirect register 190 indirect register pair 190 indirect working register 190 indirect working register pair 190 infrared encoder/decoder (IrDA) 102 Initial Uppercase Letters, Use of xvii instruction set, ez8 CPU 188
G
gated mode 74 general-purpose I/O 37 GPIO 4, 37 alternate functions 38 architecture 37 control register definitions 40 input data sample timing 180 interrupts 39 port A-C pull-up enable sub-registers 45 port A-H address registers 40 port A-H alternate function sub-registers 42 port A-H control registers 41 port A-H data direction sub-registers 42 port A-H high drive enable sub-registers 44 port A-H input data registers 46 port A-H output control sub-registers 43 port A-H output data registers 47 port A-H stop mode recovery sub-registers 44 port availability by device 37 port input timing 180 port output timing 181
H
H 191 HALT 195 halt mode 36, 195
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
225
instructions ADC 193 ADCX 193 ADD 193 ADDX 193 AND 196 ANDX 196 arithmetic 193 BCLR 194 BIT 194 bit manipulation 194 block transfer 194 BRK 196 BSET 194 BSWAP 194, 197 BTJ 196 BTJNZ 196 BTJZ 196 CALL 196 CCF 194, 195 CLR 195 COM 196 CP 193 CPC 193 CPCX 193 CPU control 195 CPX 193 DA 193 DEC 193 DECW 193 DI 195 DJNZ 196 EI 195 HALT 195 INC 193 INCW 193 IRET 196 JP 196 LD 195 LDC 195 LDCI 194, 195 LDE 195 LDEI 194 LDX 195
LEA 195 load 195 logical 196 MULT 193 NOP 195 OR 196 ORX 196 POP 195 POPX 195 program control 196 PUSH 195 PUSHX 195 RCF 194, 195 RET 196 RL 197 RLC 197 rotate and shift 197 RR 197 RRC 197 SBC 194 SCF 194, 195 SRA 197 SRL 197 SRP 195 STOP 195 SUB 194 SUBX 194 SWAP 197 TCM 194 TCMX 194 TM 194 TMX 194 TRAP 196 watch-dog timer refresh 195 XOR 196 XORX 196 instructions, eZ8 classes of 193 Intended Audience xvi interrupt control register 59 interrupt controller 5, 48 architecture 48 interrupt assertion types 51 interrupt vectors and priority 51 operation 50
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
226
register definitions 52 software interrupt assertion 51 interrupt edge select register 58 interrupt request 0 register 52 interrupt request 1 register 53 interrupt request 2 register 54 interrupt return 196 interrupt vector listing 48 interrupts not acknowledge 122 receive 122 SPI 113 transmit 122 UART 89 introduction 1 IR 190 Ir 190 IrDA architecture 102 block diagram 102 control register definitions 106 operation 103 receiving data 104 transmitting data 103 IRET 196 IRQ0 enable high and low bit registers 55 IRQ1 enable high and low bit registers 56 IRQ2 enable high and low bit registers 57 IRR 190 Irr 190
LDX 195 LEA 195 load 195 load constant 194 load constant to/from program memory 195 load constant with auto-increment addresses 195 load effective address 195 load external data 195 load external data to/from data memory and autoincrement addresses 194 load external to/from data memory and auto-increment addresses 195 load instructions 195 load using extended addressing 195 logical AND 196 logical AND/extended addressing 196 logical exclusive OR 196 logical exclusive OR/extended addressing 196 logical instructions 196 logical OR 196 logical OR/extended addressing 196 low power modes 35 LSB and MSB, Use of the Terms xvii
M
Manual Conventions xvi Manual Objectives xvi master interrupt enable 50 master-in, slave-out and-in 109 memory program 14 MISO 109 mode capture 74 capture/compare 74 continuous 73 counter 73 gated 74 one-shot 73 PWM 73 modes 74 MOSI 109 MULT 193
J
JP 196 jump, conditional, relative, and relative conditional 196
L
LD 195 LDC 195 LDCI 194, 195 LDE 195 LDEI 194, 195
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
227
multiply 193 multiprocessor mode, UART 87
N
NOP (no operation) 195 not acknowledge interrupt 122 notation b 190 cc 190 DA 190 ER 190 IM 190 IR 190 Ir 190 IRR 190 Irr 190 p 190 R 190 r 190 RA 190 RR 190 rr 190 vector 190 X 190 notational shorthand 190
O
OCD architecture 153 auto-baud detector/generator 156 baud rate limits 156 block diagram 153 breakpoints 157 commands 159 control register 163 data format 156 DBG pin to RS-232 Interface 154 debug mode 155 debugger break 196 interface 154 serial errors 157 status register 165
timing 182 OCD commands execute instruction (12H) 163 read data memory (0DH) 162 read OCD control register (05H) 161 read OCD revision (00H) 160 read OCD status register (02H) 160 read program counter (07H) 161 read program memory (0BH) 162 read program memory CRC (0EH) 163 read register (09H) 161 read runtime counter (03H) 160 step instruction (10H) 163 stuff instruction (11H) 163 write data memory (0CH) 162 write OCD control register (04H) 160 write program counter (06H) 161 write program memory (0AH) 162 write register (08H) 161 on-chip debugger 5 on-chip debugger (OCD) 153 on-chip debugger signals 10 on-chip oscillator 167 one-shot mode 73 opcode map abbreviations 209 cell description 208 first 210 second after 1FH 211 Operational Description 81 OR 196 ordering information 216 ORX 196 oscillator signals 10
P
p 190 packaging PDIP 214 Parentheses xvii Parentheses/Bracket Combinations xvii part number description 218 part selection guide 2
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
228
PC 191 PDIP 214 peripheral AC and DC electrical characteristics 177 PHASE=0 timing (SPI) 111 PHASE=1 timing (SPI) 112 pin characteristics 11 polarity 190 POP 195 pop using extended addressing 195 POPX 195 port availability, device 37 port input timing (GPIO) 180 port output timing, GPIO 181 power supply signals 11 power-down, automatic (ADC) 134 power-on and voltage brown-out 177 power-on reset (POR) 30 problem description or suggestion 221 product information 220 program control instructions 196 program counter 191 program memory 14 PUSH 195 push using extended addressing 195 PUSHX 195 PWM mode 73 PxADDR register 40 PxCTL register 41
R
R 190 r 190 RA register address 190 RCF 194, 195 receive 10-bit data format (I2C) 126 7-bit data transfer format (I2C) 125 IrDA data 104 receive interrupt 122 receiving UART data-interrupt-driven method 85 receiving UART data-polled method 85 register 118, 190
ADC control (ADCCTL) 136 ADC data high byte (ADCDH) 137 ADC data low bits (ADCDL) 138 baud low and high byte (I2C) 130, 132 baud rate high and low byte (SPI) 120 control (SPI) 115 control, I2C 129 data, SPI 114 flash control (FCTL) 145 flash high and low byte (FFREQH and FREEQL) 149 flash page select (FPS) 147 flash status (FSTAT) 146 GPIO port A-H address (PxADDR) 40 GPIO port A-H alternate function sub-registers 42 GPIO port A-H control address (PxCTL) 41 GPIO port A-H data direction sub-registers 42 I2C baud rate high (I2CBRH) 131, 132 I2C control (I2CCTL) 129 I2C data (I2CDATA) 128 I2C status 128 I2C status (I2CSTAT) 128 I2Cbaud rate low (I2CBRL) 131 mode, SPI 118 OCD control 163 OCD status 165 SPI baud rate high byte (SPIBRH) 120 SPI baud rate low byte (SPIBRL) 120 SPI control (SPICTL) 115 SPI data (SPIDATA) 115 SPI status (SPISTAT) 117 status, I2C 128 status, SPI 116 UARTx baud rate high byte (UxBRH) 99 UARTx baud rate low byte (UxBRL) 99 UARTx Control 0 (UxCTL0) 95, 98 UARTx control 1 (UxCTL1) 97 UARTx receive data (UxRXD) 93 UARTx status 0 (UxSTAT0) 93 UARTx status 1 (UxSTAT1) 95 UARTx transmit data (UxTXD) 92 watch-dog timer control (WDTCTL) 78 watch-dog timer reload high byte (WDTH) 80
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
229
watch-dog timer reload low byte (WDTL) 80 watch-dog timer reload upper byte (WDTU) 79 register file 13 register file address map 16 register pair 190 register pointer 191 reset and stop mode characteristics 29 and stop mode recovery 29 carry flag 194 controller 5 sources 30 RET 196 return 196 return information 220 RL 197 RLC 197 rotate and shift instuctions 197 rotate left 197 rotate left through carry 197 rotate right 197 rotate right through carry 197 RP 191 RR 190, 197 rr 190 RRC 197
S
Safeguards xviii SBC 194 SCF 194, 195 SCK 109 SDA and SCL (IrDA) signals 121 second opcode map after 1FH 211 serial clock 109 serial peripheral interface (SPI) 107 Set and Clear, Use of the Words xvii set carry flag 194, 195 set register pointer 195 shift right arithmatic 197 shift right logical 197 signal descriptions 9 single-sho conversion (ADC) 134
SIO 5 slave data transfer formats (I2C) 124 slave select 110 software trap 196 source operand 191 SP 191 SPI architecture 107 baud rate generator 114 baud rate high and low byte register 120 clock phase 110 configured as slave 108 control register 115 control register definitions 114 data register 114 error detection 113 interrupts 113 mode fault error 113 mode register 118 multi-master operation 112 operation 108 overrun error 113 signals 109 single master, multiple slave system 108 single master,single slave system 107 status register 116 timing, PHASE = 0 111 timing, PHASE=1 112 SPI controller signals 9 SPI mode (SPIMODE) 118 SPIBRH register 120 SPIBRL register 120 SPICTL register 115 SPIDATA register 115 SPIMODE register 118 SPISTAT register 117 SRA 197 src 191 SRL 197 SRP 195 SS, SPI signal 109 stack pointer 191 status register, I2C 128 STOP 195
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
230
stop mode 35, 195 stop mode recovery sources 33 using a GPIO port pin transition 34 using watch-dog timer time-out 33 SUB 194 subtract 194 subtract - extended addressing 194 subtract with carry 194 subtract with carry - extended addressing 194 SUBX 194 SWAP 197 swap nibbles 197 symbols, additional 191 system and core resets 30
control registers 73 high and low byte registers 69, 72 TM 194 TMX 194 tools, hardware and software 217 Trademarks xviii transmit IrDA data 103 transmit interrupt 122 transmitting UART data-polled method 83 transmitting UART dat-interrupt-driven method 84 TRAP 196
U
UART 4 architecture 81 asynchronous data format without/with parity 83 baud rate generator 91 baud rates table 100 control register definitions 92 controller signals 9 data format 82 interrupts 89 multiprocessor mode 87 receiving data using interrupt-driven method 85 receiving data using the polled method 85 transmitting data usin the interrupt-driven method 84 transmitting data using the polled method 83 x baud rate high and low registers 99 x control 0 and control 1 registers 95 x status 0 and status 1 registers 93, 95 UxBRH register 99 UxBRL register 99 UxCTL0 register 95, 98 UxCTL1 register 97 UxRXD register 93 UxSTAT0 register 93 UxSTAT1 register 95 UxTXD register 92
T
TCM 194 TCMX 194 test complement under mask 194 test complement under mask - extended addressing 194 test under mask 194 test under mask - extended addressing 194 timer signals 10 timers 5, 60 architecture 60 block diagram 61 capture mode 65, 74 capture/compare mode 68, 74 compare mode 66, 74 continuous mode 62, 73 counter mode 63 counter modes 73 gated mode 67, 74 one-shot mode 61, 73 operating mode 61 PWM mode 64, 73 reading the timer count values 69 reload high and low byte registers 70 timer control register definitions 69 timer output signal operation 69 timers 0-3
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
231
V
vector 190 voltage brown-out reset (VBR) 31
W
watch-dog timer approximate time-out delay 76 approximate time-out delays 75 CNTL 32 control register 78 electrical characteristics and timing 178 interrupt in noromal operation 76 interrupt in stop mode 76 operation 75 refresh 76, 195 reload unlock sequence 77 reload upper, high and low registers 79 reset 32 reset in normal operation 77 reset in STOP mode 77 time-out response 76 WDTCTL register 78 WDTH register 80 WDTL register 80 working register 190 working register pair 190 WTDU register 79
X
X 190 XOR 196 XORX 196
Z
Z8 Encore! block diagram 3 features 1 introduction 1 part selection guide 2
PS019707-1003
Preliminary
Index
Z8F082x/Z8F081x/Z8F042x/Z8F041x Z8 Encore!(R)
232
PS019707-1003
Preliminary
Index

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